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nvme_drv: arch-specific Dma_buffer allocation
Different cacheability properties should be applied dependent on the target architecture. genodelabs/genode#5000
This commit is contained in:
Johannes Schlatow
Christian Helmuth
parent
25ad0ad530
commit
392ed76344
42
repos/os/src/drivers/nvme/dma_buffer.h
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42
repos/os/src/drivers/nvme/dma_buffer.h
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@ -0,0 +1,42 @@
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/*
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* \brief DMA buffer utility
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* \author Johannes Schlatow
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* \date 2023-10-09
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*/
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/*
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* Copyright (C) 2023 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _NVME_DMA_BUFFER_H_
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#define _NVME_DMA_BUFFER_H_
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/* Genode includes */
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#include <platform_session/dma_buffer.h>
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namespace Util {
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using namespace Genode;
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/**
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* We use an arch-specific Dma_buffer implementation to care about
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* whether to use CACHED or UNCACHED memory.
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*/
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class Dma_buffer : public Platform::Dma_buffer
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{
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public:
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Dma_buffer(Platform::Connection &platform, size_t size);
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/**
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* If needed, we can add a method for cache clean/invalidate operations
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* that arch-specifically. Currently, the driver is used on x86 with
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* strong coherency and arm with uncached memory.
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*/
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};
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}
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#endif /* _NVME_DMA_BUFFER_H_ */
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@ -27,7 +27,6 @@
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#include <os/reporter.h>
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#include <os/session_policy.h>
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#include <platform_session/device.h>
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#include <platform_session/dma_buffer.h>
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#include <root/root.h>
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#include <timer_session/connection.h>
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#include <util/bit_array.h>
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@ -36,6 +35,7 @@
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/* local includes */
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#include <util.h>
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#include <dma_buffer.h>
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namespace {
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@ -514,7 +514,7 @@ struct Nvme::Sqe_io : Nvme::Sqe
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/*
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* Queue base structure
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*/
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struct Nvme::Queue : Platform::Dma_buffer
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struct Nvme::Queue : Util::Dma_buffer
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{
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size_t len;
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uint32_t max_entries;
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@ -523,7 +523,7 @@ struct Nvme::Queue : Platform::Dma_buffer
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uint32_t max_entries,
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size_t len)
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:
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Dma_buffer(platform, len * max_entries, UNCACHED),
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Dma_buffer(platform, len * max_entries),
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len(len), max_entries(max_entries) {};
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};
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@ -812,11 +812,11 @@ class Nvme::Controller : Platform::Device,
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Constructible<Nvme::Cq> &_admin_cq = _cq[0];
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Constructible<Nvme::Sq> &_admin_sq = _sq[0];
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Platform::Dma_buffer _nvme_identify { _platform, IDENTIFY_LEN, UNCACHED };
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Util::Dma_buffer _nvme_identify { _platform, IDENTIFY_LEN };
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Genode::Constructible<Identify_data> _identify_data { };
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Platform::Dma_buffer _nvme_nslist { _platform, IDENTIFY_LEN, UNCACHED };
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Util::Dma_buffer _nvme_nslist { _platform, IDENTIFY_LEN };
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uint32_t _nvme_nslist_count { 0 };
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size_t _mdts_bytes { 0 };
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@ -841,19 +841,19 @@ class Nvme::Controller : Platform::Device,
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SET_HMB_CID,
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};
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Constructible<Platform::Dma_buffer> _nvme_query_ns[MAX_NS] { };
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Constructible<Util::Dma_buffer> _nvme_query_ns[MAX_NS] { };
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struct Hmb_chunk
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{
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Registry<Hmb_chunk>::Element _elem;
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Platform::Dma_buffer dma_buffer;
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Util::Dma_buffer dma_buffer;
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Hmb_chunk(Registry<Hmb_chunk> ®istry,
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Platform::Connection &platform, size_t size)
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:
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_elem { registry, *this },
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dma_buffer { platform, size, UNCACHED }
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dma_buffer { platform, size }
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{ }
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virtual ~Hmb_chunk() { }
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@ -875,7 +875,7 @@ class Nvme::Controller : Platform::Device,
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Heap _hmb_alloc { _env.ram(), _env.rm() };
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Constructible<Hmb_chunk_registry> _hmb_chunk_registry { };
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Constructible<Platform::Dma_buffer> _hmb_descr_list_buffer { };
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Constructible<Util::Dma_buffer> _hmb_descr_list_buffer { };
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Info _info { };
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@ -1103,7 +1103,7 @@ class Nvme::Controller : Platform::Device,
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uint16_t const id = 0;
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if (!_nvme_query_ns[id].constructed())
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_nvme_query_ns[id].construct(_platform, IDENTIFY_LEN, UNCACHED);
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_nvme_query_ns[id].construct(_platform, IDENTIFY_LEN);
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Sqe_identify b(_admin_command(Opcode::IDENTIFY, ns[id], QUERYNS_CID));
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b.write<Nvme::Sqe::Prp1>(_nvme_query_ns[id]->dma_addr());
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@ -1222,7 +1222,7 @@ class Nvme::Controller : Platform::Device,
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uint32_t const num_entries = bytes / HMB_CHUNK_SIZE;
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try {
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_hmb_descr_list_buffer.construct(_platform, HMB_LIST_SIZE, UNCACHED);
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_hmb_descr_list_buffer.construct(_platform, HMB_LIST_SIZE);
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} catch (... /* intentional catch-all */) {
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warning("could not allocate HMB descriptor list page");
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return;
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@ -1771,14 +1771,13 @@ class Nvme::Driver : Genode::Noncopyable
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** DMA **
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*********/
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Constructible<Platform::Dma_buffer> _dma_buffer { };
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Constructible<Util::Dma_buffer> _dma_buffer { };
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/*
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* The PRP (Physical Region Pages) page is used to setup
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* large requests.
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*/
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Platform::Dma_buffer _prp_list_helper { _platform, Nvme::PRP_DS_SIZE,
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UNCACHED };
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Util::Dma_buffer _prp_list_helper { _platform, Nvme::PRP_DS_SIZE };
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/***********
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** Block **
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@ -2162,7 +2161,7 @@ class Nvme::Driver : Genode::Noncopyable
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Dataspace_capability dma_buffer_construct(size_t size)
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{
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_dma_buffer.construct(_platform, size, UNCACHED);
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_dma_buffer.construct(_platform, size);
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return _dma_buffer->cap();
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}
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19
repos/os/src/drivers/nvme/spec/arm_64/dma_buffer.cc
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19
repos/os/src/drivers/nvme/spec/arm_64/dma_buffer.cc
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@ -0,0 +1,19 @@
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/*
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* \brief ARM 64bit DMA buffer
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* \author Johannes Schlatow
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* \date 2023-10-09
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*/
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/*
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* Copyright (C) 2023 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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/* local includes */
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#include <dma_buffer.h>
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Util::Dma_buffer::Dma_buffer(Platform::Connection &platform, Genode::size_t size)
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: Platform::Dma_buffer(platform, size, Genode::UNCACHED)
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{ }
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4
repos/os/src/drivers/nvme/spec/arm_64/target.mk
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4
repos/os/src/drivers/nvme/spec/arm_64/target.mk
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@ -0,0 +1,4 @@
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include $(PRG_DIR)/../../target.inc
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REQUIRES += arm_64
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SRC_CC += spec/arm_64/dma_buffer.cc
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19
repos/os/src/drivers/nvme/spec/x86/dma_buffer.cc
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19
repos/os/src/drivers/nvme/spec/x86/dma_buffer.cc
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@ -0,0 +1,19 @@
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/*
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* \brief x86 DMA buffer
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* \author Johannes Schlatow
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* \date 2023-10-09
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*/
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/*
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* Copyright (C) 2023 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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/* local includes */
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#include <dma_buffer.h>
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Util::Dma_buffer::Dma_buffer(Platform::Connection &platform, Genode::size_t size)
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: Platform::Dma_buffer(platform, size, UNCACHED)
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{ }
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4
repos/os/src/drivers/nvme/spec/x86/target.mk
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4
repos/os/src/drivers/nvme/spec/x86/target.mk
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include $(PRG_DIR)/../../target.inc
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REQUIRES += x86
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SRC_CC += spec/x86/dma_buffer.cc
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6
repos/os/src/drivers/nvme/target.inc
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6
repos/os/src/drivers/nvme/target.inc
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TARGET = nvme_drv
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SRC_CC = main.cc
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INC_DIR += $(PRG_DIR)/../.. $(PRG_DIR)
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LIBS += base
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vpath %.cc $(PRG_DIR)/../..
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@ -1,4 +0,0 @@
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TARGET = nvme_drv
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SRC_CC = main.cc
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INC_DIR += $(PRG_DIR)
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LIBS += base
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