diff --git a/repos/dde_ipxe/patches/intel.patch b/repos/dde_ipxe/patches/intel.patch
index 5a7d1c6bd5..d8e299cd3d 100644
--- a/repos/dde_ipxe/patches/intel.patch
+++ b/repos/dde_ipxe/patches/intel.patch
@@ -18,6 +18,30 @@
 +	PCI_ROM ( 0x8086, 0x155a, "i218lm", "I218LM", 0 ),
 +	PCI_ROM ( 0x8086, 0x15a2, "i218lm-3", "I218-LM", 0 ),
 +	PCI_ROM ( 0x8086, 0x156f, "i219lm", "I219-LM", 0 ),
- 	PCI_ROM ( 0x8086, 0x294c, "82566dc-2", "82566DC-2", 0 ),
+	PCI_ROM ( 0x8086, 0x294c, "82566dc-2", "82566DC-2", 0 ),
  	PCI_ROM ( 0x8086, 0x2e6e, "cemedia", "CE Media Processor", 0 ),
  };
+--- a/src/drivers/net/intel.h
++++ b/src/drivers/net/intel.h
+@@ -138,10 +138,10 @@ enum intel_descriptor_status {
+  * Minimum value is 8, since the descriptor ring length must be a
+  * multiple of 128.
+  */
+-#define INTEL_NUM_RX_DESC 8
++#define INTEL_NUM_RX_DESC 256
+ 
+ /** Receive descriptor ring fill level */
+-#define INTEL_RX_FILL 4
++#define INTEL_RX_FILL (INTEL_NUM_RX_DESC / 2)
+ 
+ /** Receive buffer length */
+ #define INTEL_RX_MAX_LEN 2048
+@@ -154,7 +154,7 @@ enum intel_descriptor_status {
+  * Descriptor ring length must be a multiple of 16.  ICH8/9/10
+  * requires a minimum of 16 TX descriptors.
+  */
+-#define INTEL_NUM_TX_DESC 16
++#define INTEL_NUM_TX_DESC 256
+ 
+ /** Receive/Transmit Descriptor Base Address Low (offset) */
+ #define INTEL_xDBAL 0x00
diff --git a/repos/dde_ipxe/ports/dde_ipxe.hash b/repos/dde_ipxe/ports/dde_ipxe.hash
index d04e61538c..c1753d0686 100644
--- a/repos/dde_ipxe/ports/dde_ipxe.hash
+++ b/repos/dde_ipxe/ports/dde_ipxe.hash
@@ -1 +1 @@
-07dd65ccba7d9b1f98579fcf0d0755dc8a53e1a4
+3bdff36769bbe70cc2d711b3ca4e00536a0e51da