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hw: l2 cache initialization is platform specific
On ARM Cortex A9 platforms the external PL310 L2 cache controller needs to be initialized dependent on the SoC. For instance on Pandaboard it needs to call the firmware running in TrustZone's secure world, on i.MX6 it initializes it directly, on other boards it doesn't need to be initialized at all, because the bootloader already did so. Therefore, we should implement the PL310 intialization in board specific code and not in the base class implementation. Ref #1312
This commit is contained in:
Stefan Kalkowski
Christian Helmuth
parent
e05d26567d
commit
166672fe16
@ -21,80 +21,59 @@
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namespace Arm
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{
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using Genode::addr_t;
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class Pl310;
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struct Pl310;
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}
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/**
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* L2 outer cache controller
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*/
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class Arm::Pl310 : Genode::Mmio
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struct Arm::Pl310 : Genode::Mmio
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{
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protected:
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struct Control : Register <0x100, 32>
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{
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struct Enable : Bitfield<0,1> { };
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};
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struct Control : Register <0x100, 32>
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{
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struct Enable : Bitfield<0,1> { };
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};
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struct Aux : Register<0x104, 32>
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{
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struct Associativity : Bitfield<16,1> { };
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struct Way_size : Bitfield<17,3> { };
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struct Share_override : Bitfield<22,1> { };
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struct Reserved : Bitfield<25,1> { };
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struct Ns_lockdown : Bitfield<26,1> { };
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struct Ns_irq_ctrl : Bitfield<27,1> { };
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struct Data_prefetch : Bitfield<28,1> { };
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struct Inst_prefetch : Bitfield<29,1> { };
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struct Early_bresp : Bitfield<30,1> { };
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};
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struct Aux : Register<0x104, 32>
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{
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struct Associativity : Bitfield<16,1> { };
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struct Way_size : Bitfield<17,3> { };
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struct Share_override : Bitfield<22,1> { };
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struct Reserved : Bitfield<25,1> { };
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struct Ns_lockdown : Bitfield<26,1> { };
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struct Ns_irq_ctrl : Bitfield<27,1> { };
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struct Data_prefetch : Bitfield<28,1> { };
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struct Inst_prefetch : Bitfield<29,1> { };
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struct Early_bresp : Bitfield<30,1> { };
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struct Irq_mask : Register <0x214, 32> { };
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struct Irq_clear : Register <0x220, 32> { };
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struct Cache_sync : Register <0x730, 32> { };
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struct Invalidate_by_way : Register <0x77c, 32> { };
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struct Clean_invalidate_by_way : Register <0x7fc, 32> { };
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static access_t init_value()
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{
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access_t v = 0;
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Associativity::set(v, 1);
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Way_size::set(v, 3);
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Share_override::set(v, 1);
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Reserved::set(v, 1);
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Ns_lockdown::set(v, 1);
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Ns_irq_ctrl::set(v, 1);
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Data_prefetch::set(v, 1);
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Inst_prefetch::set(v, 1);
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Early_bresp::set(v, 1);
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return v;
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}
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};
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Pl310(Genode::addr_t const base) : Mmio(base) { }
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struct Irq_mask : Register <0x214, 32> { };
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struct Irq_clear : Register <0x220, 32> { };
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struct Cache_sync : Register <0x730, 32> { };
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struct Invalidate_by_way : Register <0x77c, 32> { };
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struct Clean_invalidate_by_way : Register <0x7fc, 32> { };
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inline void sync() { while (read<Cache_sync>()) ; }
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inline void _sync() { while (read<Cache_sync>()) ; }
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void flush()
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{
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write<Clean_invalidate_by_way>((1UL << 16) - 1);
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sync();
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}
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void _init()
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{
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write<Irq_mask>(0);
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write<Irq_clear>(~0);
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}
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void invalidate()
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{
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write<Invalidate_by_way>((1UL << 16) - 1);
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sync();
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}
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public:
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Pl310(addr_t const base) : Mmio(base) { }
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void flush()
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{
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write<Clean_invalidate_by_way>((1 << 16) - 1);
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_sync();
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}
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void invalidate()
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{
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write<Invalidate_by_way>((1 << 16) - 1);
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_sync();
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}
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void mask_interrupts()
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{
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write<Irq_mask>(0);
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write<Irq_clear>(~0UL);
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}
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};
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#endif /* _SPEC__ARM__PL310_H_ */
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@ -21,50 +21,68 @@
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namespace Genode
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{
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class Pl310;
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class L2_cache;
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class Board;
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}
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/**
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* L2 outer cache controller
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*/
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class Genode::Pl310 : public Arm::Pl310
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class Genode::L2_cache
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{
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private:
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enum Secure_monitor_syscalls
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struct Secure_monitor
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{
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L2_CACHE_SET_DEBUG_REG = 0x100,
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L2_CACHE_ENABLE_REG = 0x102,
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L2_CACHE_AUX_REG = 0x109,
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};
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enum Syscalls
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{
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L2_CACHE_SET_DEBUG_REG = 0x100,
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L2_CACHE_ENABLE_REG = 0x102,
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L2_CACHE_AUX_REG = 0x109,
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};
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static inline void _secure_monitor_call(addr_t func, addr_t val)
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{
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register addr_t _func asm("r12") = func;
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register addr_t _val asm("r0") = val;
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asm volatile(
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"dsb; smc #0" ::
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"r" (_func), "r" (_val) :
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"memory", "cc", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11");
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}
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void call(addr_t func, addr_t val)
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{
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register addr_t _func asm("r12") = func;
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register addr_t _val asm("r0") = val;
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asm volatile(
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"dsb; smc #0" ::
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"r" (_func), "r" (_val) :
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"memory", "cc", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11");
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}
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} _secure_monitor;
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Arm::Pl310 _pl310;
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public:
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void flush()
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L2_cache() : _pl310(Cortex_a9::Board::PL310_MMIO_BASE)
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{
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_secure_monitor_call(L2_CACHE_SET_DEBUG_REG, 0x3);
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Arm::Pl310::flush();
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_secure_monitor_call(L2_CACHE_SET_DEBUG_REG, 0x0);
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Arm::Pl310::Aux::access_t v = 0;
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Arm::Pl310::Aux::Associativity::set(v, 1);
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Arm::Pl310::Aux::Way_size::set(v, 3);
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Arm::Pl310::Aux::Share_override::set(v, 1);
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Arm::Pl310::Aux::Reserved::set(v, 1);
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Arm::Pl310::Aux::Ns_lockdown::set(v, 1);
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Arm::Pl310::Aux::Ns_irq_ctrl::set(v, 1);
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Arm::Pl310::Aux::Data_prefetch::set(v, 1);
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Arm::Pl310::Aux::Inst_prefetch::set(v, 1);
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Arm::Pl310::Aux::Early_bresp::set(v, 1);
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_secure_monitor.call(Secure_monitor::L2_CACHE_AUX_REG, v);
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_secure_monitor.call(Secure_monitor::L2_CACHE_ENABLE_REG, 1);
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_pl310.mask_interrupts();
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}
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Pl310(addr_t const base) : Arm::Pl310(base)
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void flush()
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{
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_secure_monitor_call(L2_CACHE_AUX_REG, Aux::init_value());
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_secure_monitor_call(L2_CACHE_ENABLE_REG, 1);
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_init();
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_secure_monitor.call(Secure_monitor::L2_CACHE_SET_DEBUG_REG, 0x3);
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_pl310.flush();
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_secure_monitor.call(Secure_monitor::L2_CACHE_SET_DEBUG_REG, 0x0);
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}
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void invalidate() { _pl310.invalidate(); }
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};
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/**
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@ -33,7 +33,7 @@ class Genode::Pl310 : public Arm::Pl310
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{
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public:
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Pl310(addr_t const base) : Arm::Pl310(base) { _init(); }
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Pl310(addr_t const base) : Arm::Pl310(base) { mask_interrupts(); }
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};
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/**
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@ -62,8 +62,8 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i)
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}
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static Genode::Pl310 * l2_cache() {
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return unmanaged_singleton<Genode::Pl310>(Board::PL310_MMIO_BASE); }
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static Genode::L2_cache * l2_cache() {
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return unmanaged_singleton<Genode::L2_cache>(); }
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void Board::outer_cache_invalidate() { l2_cache()->invalidate(); }
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