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mesa/iris: remove binder patch

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There is one binder with one memory zone per OpenGL context. The patch was
needed before because Genode didn't have proper context support (separate page
tables) leading to binders from one or more context being allocated to the same
GPU address with the same page tables. This was clearly an error and is fixed
with context support.

issue #4664
This commit is contained in:
Sebastian Sumpf 2022-11-08 14:44:39 +01:00 committed by Christian Helmuth
parent c0367fc30e
commit 0b569ed8c7
3 changed files with 1 additions and 28 deletions
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2
repos/libports/ports/mesa.hash
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@ -1 +1 @@
a195203391df18dabe0e9c247301d9f3df1c8192
5762ad18c4b5d48ad6b8651fc554e65d656e144f

1
repos/libports/ports/mesa.port
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@ -18,7 +18,6 @@ PATCHES := src/lib/mesa/patches/bitset_redefined.patch \
src/lib/mesa/patches/iris.patch \
src/lib/mesa/patches/iris_bufmgr_tmp.patch \
src/lib/mesa/patches/iris_bufmgr_unmap.patch \
src/lib/mesa/patches/iris_binder.patch \
src/lib/mesa/patches/iris_disable_compute.patch \
src/lib/mesa/patches/lseek.patch \
src/lib/mesa/patches/mesa.patch \

26
repos/libports/src/lib/mesa/patches/iris_binder.patch
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@ -1,26 +0,0 @@
The binder re-uses vgpu addresses of buffer objects, which are scheduled
to be deleted, but not yet destroyed. The drm_ioctl backend still have a
vgpu mapping of the not yet destroyed buffer object. When the binder reuses
the vgpu address for a new/another buffer object, the gpu multiplexer will
complain about an overmap. To avoid that, as workaround, don't reuse vgpu
addresses immediately in the binder.
--- a/src/lib/mesa/src/gallium/drivers/iris/iris_binder.c
+++ a/src/lib/mesa/src/gallium/drivers/iris/iris_binder.c
@@ -71,7 +71,7 @@
struct iris_bufmgr *bufmgr = screen->bufmgr;
struct iris_binder *binder = &ice->state.binder;
- uint64_t next_address = IRIS_MEMZONE_BINDER_START;
+ static uint64_t next_address = IRIS_MEMZONE_BINDER_START;
if (binder->bo) {
/* Place the new binder just after the old binder, unless we've hit the
@@ -100,6 +100,8 @@
*/
ice->state.dirty |= IRIS_DIRTY_RENDER_BUFFER;
ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS;
+
+ next_address += IRIS_BINDER_SIZE;
}
static uint32_t