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https://github.com/genodelabs/genode.git
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platform_drv: add EHCI PCI quirk, apply in order
* Add EHCI PCI quirk * Add UHCI reset to UHCI quirk * Apply all PCI quirks in order of the PCI bus numbering otherwise the machine might stall Ref genodelabs/genode#4578
This commit is contained in:
Stefan Kalkowski
Christian Helmuth
parent
a77ceb6871
commit
00c9ac363f
@ -205,4 +205,11 @@ void Driver::Device_model::generate(Xml_generator & xml) const
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void Driver::Device_model::update(Xml_node const & node)
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{
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_model.update_from_xml(*this, node);
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/*
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* Iterate over all devices and apply PCI quirks if necessary
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*/
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for_each([&] (Device const & device) {
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pci_apply_quirks(_env, device);
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});
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}
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@ -19,6 +19,7 @@
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#include <device_pd.h>
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#include <pci.h>
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#include <pci_uhci.h>
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#include <pci_ehci.h>
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#include <pci_intel_graphics.h>
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#include <pci_hd_audio.h>
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#include <pci_virtio.h>
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@ -29,16 +30,17 @@ using namespace Pci;
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struct Config_helper
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{
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Env & _env;
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Driver::Device const & _dev;
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Driver::Device::Pci_config const & _cfg;
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Attached_io_mem_dataspace _io_mem;
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Attached_io_mem_dataspace _io_mem { _env, _cfg.addr, 0x1000 };
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Config _config { (addr_t)_io_mem.local_addr<void>() };
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Config_helper(Env & env,
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Driver::Device const & dev,
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Driver::Device::Pci_config const & cfg)
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: _dev(dev), _cfg(cfg), _io_mem(env, cfg.addr, 0x1000) { }
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: _env(env), _dev(dev), _cfg(cfg) { }
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void enable(Driver::Device_pd & pd)
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{
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@ -62,10 +64,6 @@ struct Config_helper
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Config::Command::Io_space_enable::set(cmd, 1); });
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_config.write<Config::Command>(cmd);
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/* apply different PCI quirks, bios handover etc. */
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Driver::pci_uhci_quirks(_cfg, _config.base());
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Driver::pci_hd_audio_quirks(_cfg, _config);
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}
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void disable()
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@ -78,6 +76,32 @@ struct Config_helper
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Config::Command::Interrupt_enable::set(cmd, 0);
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_config.write<Config::Command>(cmd);
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}
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void apply_quirks()
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{
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Config::Command::access_t cmd =
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_config.read<Config::Command>();
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Config::Command::access_t cmd_old = cmd;
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/* enable memory space when I/O mem is defined */
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_dev.for_each_io_mem([&] (unsigned, Driver::Device::Io_mem::Range,
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Driver::Device::Pci_bar, bool) {
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Config::Command::Memory_space_enable::set(cmd, 1); });
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/* enable i/o space when I/O ports are defined */
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_dev.for_each_io_port_range(
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[&] (unsigned, Driver::Device::Io_port_range::Range) {
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Config::Command::Io_space_enable::set(cmd, 1); });
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_config.write<Config::Command>(cmd);
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/* apply different PCI quirks, bios handover etc. */
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Driver::pci_uhci_quirks(_env, _dev, _cfg, _config.base());
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Driver::pci_ehci_quirks(_env, _dev, _cfg, _config.base());
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Driver::pci_hd_audio_quirks(_cfg, _config);
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_config.write<Config::Command>(cmd_old);
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}
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};
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@ -95,6 +119,13 @@ void Driver::pci_disable(Env & env, Device const & dev)
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}
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void Driver::pci_apply_quirks(Env & env, Device const & dev)
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{
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dev.for_pci_config([&] (Device::Pci_config const & pc) {
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Config_helper(env, dev, pc).apply_quirks(); });
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}
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void Driver::pci_msi_enable(Env & env,
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addr_t cfg_space,
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Irq_session::Info const info)
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@ -24,6 +24,7 @@ namespace Driver {
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void pci_enable(Genode::Env & env, Device_pd & pd, Device const & dev);
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void pci_disable(Genode::Env & env, Device const & dev);
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void pci_apply_quirks(Genode::Env & env, Device const & dev);
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void pci_msi_enable(Genode::Env & env, addr_t cfg_space,
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Genode::Irq_session::Info const info);
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bool pci_device_matches(Genode::Session_policy const & policy,
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105
repos/os/src/drivers/platform/pci_ehci.h
Normal file
105
repos/os/src/drivers/platform/pci_ehci.h
Normal file
@ -0,0 +1,105 @@
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/*
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* \brief Platform driver - PCI EHCI utilities
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* \author Stefan Kalkowski
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* \date 2022-09-28
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*/
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/*
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* Copyright (C) 2022 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <pci/config.h>
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#include <device.h>
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namespace Driver {
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static void pci_ehci_quirks(Env &, Device const &,
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Device::Pci_config, addr_t);
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}
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void Driver::pci_ehci_quirks(Env & env,
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Device const & dev,
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Device::Pci_config cfg,
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addr_t base)
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{
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enum { EHCI_CLASS_CODE = 0xc0320 };
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if (cfg.class_code != EHCI_CLASS_CODE)
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return;
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/* EHCI host controller register definitions */
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struct Ehci : Mmio
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{
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struct Capability_parameters : Register<0x8, 32>
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{
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struct Extended_cap_pointer : Bitfield<8,8> {};
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};
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struct Configure_flag : Register<0x40, 32> {};
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using Mmio::Mmio;
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};
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struct Ehci_pci : Mmio
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{
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struct Port_wake : Register<0x62, 16> {};
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using Mmio::Mmio;
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};
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/* PCI extended capability for EHCI */
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struct Cap : Mmio
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{
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struct Pointer : Register<0x0, 16>
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{
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struct Id : Bitfield<0, 8> { enum { SYNC = 1 }; };
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struct Next : Bitfield<8, 8> { };
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};
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struct Bios_semaphore : Register<0x2, 8> { };
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struct Os_semaphore : Register<0x3, 8> { };
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struct Usb_legacy_control_status : Register<0x4, 32> {};
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using Mmio::Mmio;
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};
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/* find ehci controller registers behind PCI bar zero */
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dev.for_each_io_mem([&] (unsigned, Device::Io_mem::Range range,
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Device::Pci_bar bar, bool)
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{
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if (!bar.valid() || bar.number != 0)
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return;
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Ehci_pci pw(base);
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Attached_io_mem_dataspace iomem(env, range.start, 0x1000);
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Ehci ehci((addr_t)iomem.local_addr<void>());
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addr_t offset =
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ehci.read<Ehci::Capability_parameters::Extended_cap_pointer>();
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/* iterate over EHCI extended capabilities */
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while (offset) {
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Cap cap(base + offset);
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if (cap.read<Cap::Pointer::Id>() != Cap::Pointer::Id::SYNC)
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break;
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bool bios_owned = cap.read<Cap::Bios_semaphore>();
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if (bios_owned) cap.write<Cap::Os_semaphore>(1);
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enum { MAX_ROUNDS = 1000000 };
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unsigned rounds = MAX_ROUNDS;
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while (cap.read<Cap::Bios_semaphore>() && --rounds) ;
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if (!rounds) cap.write<Cap::Bios_semaphore>(0);
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cap.write<Cap::Usb_legacy_control_status>(0);
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if (bios_owned) ehci.write<Ehci::Configure_flag>(0);
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offset = cap.read<Cap::Pointer::Next>();
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}
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});
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}
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@ -11,15 +11,20 @@
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <io_port_session/connection.h>
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#include <pci/config.h>
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#include <device.h>
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namespace Driver {
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static void pci_uhci_quirks(Device::Pci_config cfg, addr_t base);
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static void pci_uhci_quirks(Env &, Device const &,
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Device::Pci_config, addr_t);
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}
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void Driver::pci_uhci_quirks(Device::Pci_config cfg, addr_t base)
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void Driver::pci_uhci_quirks(Env & env,
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Device const & dev,
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Device::Pci_config cfg,
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addr_t base)
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{
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enum { UHCI_CLASS_CODE = 0xc0300 };
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@ -44,20 +49,70 @@ void Driver::pci_uhci_quirks(Device::Pci_config cfg, addr_t base)
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using Mmio::Mmio;
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};
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/* find uhci controller i/o ports */
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Device::Io_port_range::Range range { 0, 0 };
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dev.for_each_io_port_range([&] (unsigned, Device::Io_port_range::Range r) {
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if (!range.size) range = r; });
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Io_port_connection io_ports(env, range.addr, range.size);
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Uhci config(base);
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bool have_to_reset = false;
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uint16_t UHCI_CMD = range.addr;
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uint16_t UHCI_INTR = range.addr + 4;
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struct Uhci_command : Register<16>
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{
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struct Enable : Bitfield<0,1> {};
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struct Reset : Bitfield<1,1> {};
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struct Global_suspend : Bitfield<3,1> {};
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struct Config : Bitfield<6,1> {};
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};
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struct Uhci_irq_status : Register<16>
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{
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struct Resume : Bitfield<1,1> {};
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};
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using Reg = Uhci::Usb_legacy_support;
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/* BIOS handover */
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/***************************
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** BIOS handover + reset **
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***************************/
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Reg::access_t reg = 0;
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Reg::Trap_by_60h_read_status::set(reg,1);
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Reg::Trap_by_60h_write_status::set(reg,1);
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Reg::Trap_by_64h_read_status::set(reg,1);
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Reg::Trap_by_64h_write_status::set(reg,1);
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Reg::End_of_a20gate_pass_through_status::set(reg,1);
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Reg::Usb_pirq_enable::set(reg,1);
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if (config.read<Reg>() & ~reg)
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have_to_reset = true;
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if (!have_to_reset) {
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Uhci_command::access_t cmd = io_ports.inw(UHCI_CMD);
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if (Uhci_command::Enable::get(cmd) ||
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!Uhci_command::Config::get(cmd) ||
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!Uhci_command::Global_suspend::get(cmd))
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have_to_reset = true;
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}
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if (!have_to_reset) {
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Uhci_irq_status::access_t intr = io_ports.inw(UHCI_INTR);
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if (intr & ~Uhci_irq_status::Resume::mask())
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have_to_reset = true;
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}
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if (!have_to_reset)
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return;
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config.write<Reg>(reg);
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io_ports.outw(UHCI_CMD, Uhci_command::Reset::bits(1));
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io_ports.outw(UHCI_INTR, 0);
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io_ports.outw(UHCI_CMD, 0);
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if (cfg.vendor_id == 0x8086)
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config.write<Uhci::Usb_resume_intel>(0);
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}
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