2017-12-07 10:17:39 +00:00
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diff --git a/src/drivers/net/intel.c b/src/drivers/net/intel.c
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index c3a7d407..8e8cea67 100644
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--- a/src/drivers/net/intel.c
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2014-08-01 15:16:38 +00:00
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+++ b/src/drivers/net/intel.c
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2016-01-28 10:10:17 +00:00
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@@ -305,6 +305,9 @@ static int intel_reset ( struct intel_nic *intel ) {
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return 0;
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}
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+ /* XXX skip MAC/PHY reset */
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+ return 0;
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+
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/* Reset PHY and MAC simultaneously */
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writel ( ( ctrl | INTEL_CTRL_RST | INTEL_CTRL_PHY_RST ),
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intel->regs + INTEL_CTRL );
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2017-12-07 10:17:39 +00:00
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@@ -953,6 +956,13 @@ static struct pci_device_id intel_nics[] = {
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2014-08-01 15:16:38 +00:00
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PCI_ROM ( 0x8086, 0x1526, "82576-5", "82576", 0 ),
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PCI_ROM ( 0x8086, 0x1527, "82580-f2", "82580 Fiber", 0 ),
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PCI_ROM ( 0x8086, 0x1533, "i210", "I210", 0 ),
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+ PCI_ROM ( 0x8086, 0x153a, "i217lm", "I217LM", 0 ),
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2014-09-08 09:53:54 +00:00
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+ PCI_ROM ( 0x8086, 0x1559, "i218v", "I218V", 0 ),
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+ PCI_ROM ( 0x8086, 0x155a, "i218lm", "I218LM", 0 ),
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2015-10-28 15:14:15 +00:00
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+ PCI_ROM ( 0x8086, 0x15a2, "i218lm-3", "I218-LM", 0 ),
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2016-05-24 08:22:20 +00:00
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+ PCI_ROM ( 0x8086, 0x156f, "i219lm", "I219-LM", 0 ),
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2017-11-02 20:38:05 +00:00
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+ PCI_ROM ( 0x8086, 0x15b7, "i219lm", "I219-LM", 0 ),
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2017-12-07 10:17:39 +00:00
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+ PCI_ROM ( 0x8086, 0x1570, "i219v", "I219V", 0 ),
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PCI_ROM ( 0x8086, 0x294c, "82566dc-2", "82566DC-2", 0 ),
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2014-08-01 15:16:38 +00:00
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PCI_ROM ( 0x8086, 0x2e6e, "cemedia", "CE Media Processor", 0 ),
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};
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2017-12-07 10:17:39 +00:00
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diff --git a/src/drivers/net/intel.h b/src/drivers/net/intel.h
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index 20b4255e..2a11e1df 100644
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2016-09-17 17:10:51 +00:00
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--- a/src/drivers/net/intel.h
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+++ b/src/drivers/net/intel.h
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@@ -138,10 +138,10 @@ enum intel_descriptor_status {
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* Minimum value is 8, since the descriptor ring length must be a
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* multiple of 128.
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*/
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-#define INTEL_NUM_RX_DESC 8
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+#define INTEL_NUM_RX_DESC 256
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/** Receive descriptor ring fill level */
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-#define INTEL_RX_FILL 4
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+#define INTEL_RX_FILL (INTEL_NUM_RX_DESC / 2)
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/** Receive buffer length */
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#define INTEL_RX_MAX_LEN 2048
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@@ -154,7 +154,7 @@ enum intel_descriptor_status {
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* Descriptor ring length must be a multiple of 16. ICH8/9/10
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* requires a minimum of 16 TX descriptors.
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*/
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-#define INTEL_NUM_TX_DESC 16
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+#define INTEL_NUM_TX_DESC 256
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/** Receive/Transmit Descriptor Base Address Low (offset) */
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#define INTEL_xDBAL 0x00
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