genode/repos/base-hw/lib/mk/spec/riscv/bootstrap-hw-spike.mk

#
# evaluate bbl_dir immediately, otherwise it won't recognize
# missing ports when checking library dependencies
#
BBL_DIR := $(call select_from_ports,bbl)/src/lib/bbl

INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/riscv $(BBL_DIR)

SRC_CC  += bootstrap/spec/riscv/platform.cc
SRC_CC  += lib/base/riscv/kernel/interface.cc
SRC_CC  += spec/64bit/memory_map.cc
SRC_S   += bootstrap/spec/riscv/crt0.s

vpath spec/64bit/memory_map.cc $(BASE_DIR)/../base-hw/src/lib/hw

include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
hw_riscv: strictly separate machine and syscall ids Fix #3230 2019-03-14 14:33:32 +00:00			`#`
			`# evaluate bbl_dir immediately, otherwise it won't recognize`
			`# missing ports when checking library dependencies`
			`#`
			`BBL_DIR := $(call select_from_ports,bbl)/src/lib/bbl`

			`INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/riscv $(BBL_DIR)`
hw: bootstrap into kernel Put the initialization of the cpu cores, setup of page-tables, enabling of MMU and caches into a separate component that is only used to bootstrap the kernel resp. core. Ref #2092 2016-11-07 17:00:24 +00:00
			`SRC_CC += bootstrap/spec/riscv/platform.cc`
			`SRC_CC += lib/base/riscv/kernel/interface.cc`
hw: introduce kernel/user address space split * introduces central memory map for core/kernel * on 32-bit platforms the kernel/core starts at 0x80000000 * on 64-bit platforms the kernel/core starts at 0xffffffc000000000 * mark kernel/core mappings as global ones (tagged TLB) * move the exception vector to begin of core's binary, thereby bootstrap knows from where to map it appropriately * do not map boot modules into core anymore * constrain core's virtual heap memory area * differentiate in between user's and core's main thread's UTCB, which now resides inside the kernel segment Ref #2091 2017-06-20 13:25:04 +00:00			`SRC_CC += spec/64bit/memory_map.cc`
hw: bootstrap into kernel Put the initialization of the cpu cores, setup of page-tables, enabling of MMU and caches into a separate component that is only used to bootstrap the kernel resp. core. Ref #2092 2016-11-07 17:00:24 +00:00			`SRC_S += bootstrap/spec/riscv/crt0.s`

hw: introduce kernel/user address space split * introduces central memory map for core/kernel * on 32-bit platforms the kernel/core starts at 0x80000000 * on 64-bit platforms the kernel/core starts at 0xffffffc000000000 * mark kernel/core mappings as global ones (tagged TLB) * move the exception vector to begin of core's binary, thereby bootstrap knows from where to map it appropriately * do not map boot modules into core anymore * constrain core's virtual heap memory area * differentiate in between user's and core's main thread's UTCB, which now resides inside the kernel segment Ref #2091 2017-06-20 13:25:04 +00:00			`vpath spec/64bit/memory_map.cc $(BASE_DIR)/../base-hw/src/lib/hw`

hw: bootstrap into kernel Put the initialization of the cpu cores, setup of page-tables, enabling of MMU and caches into a separate component that is only used to bootstrap the kernel resp. core. Ref #2092 2016-11-07 17:00:24 +00:00			`include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc`