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genode/repos/base/include/spec/imx6/drivers/board_base.h

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hw: support Wandboard Quad (i.MX6) The port uses the Cortex-A9 private timer for the kernel and an EPIT as user timer. It was successfully tested on the Wandboard Quad and the CuBox-i with the signal test. It lacks L2-cache and Trustzone support by now. Thanks to Praveen Srinivas (IIT Madras, India) and Nikolay Golikov (Ksys Labs LLC, Russia). This work is partially based on their contributions. Fix #1467
2015-03-25 18:30:37 +00:00
/*
* \brief Board definitions for the Freescale i.MX6
* \author Nikolay Golikov <nik@ksyslabs.org>
* \author Josef Soentgen
* \author Martin Stein
* \date 2014-02-25
*/
/*
hw: enable SMP for ARM Cortex A9 This commit enables multi-processing for all Cortex A9 SoCs we currently support. Moreover, it thereby enables the L2 cache for i.MX6 that was not enabled until now. However, the QEMU variants hw_pbxa9 and hw_zynq still only use 1 core, because the busy cpu synchronization used when initializing multiple Cortex A9 cores leads to horrible boot times on QEMU. During this work the CPU initialization in general was reworked. From now on lots of hardware specifics were put into the 'spec' specific files, some generic hook functions and abstractions thereby were eliminated. This results to more lean implementations for instance on non-SMP platforms, or in the x86 case where cache maintainance is a non-issue. Due to the fact that memory/cache coherency and SMP are closely coupled on ARM Cortex A9 this commit combines so different aspects. Fix #1312 Fix #1807
2016-01-11 10:02:52 +00:00
* Copyright (C) 2014-2016 Ksys Labs LLC
* Copyright (C) 2014-2016 Genode Labs GmbH
hw: support Wandboard Quad (i.MX6) The port uses the Cortex-A9 private timer for the kernel and an EPIT as user timer. It was successfully tested on the Wandboard Quad and the CuBox-i with the signal test. It lacks L2-cache and Trustzone support by now. Thanks to Praveen Srinivas (IIT Madras, India) and Nikolay Golikov (Ksys Labs LLC, Russia). This work is partially based on their contributions. Fix #1467
2015-03-25 18:30:37 +00:00
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
Introduce 'spec' subdirectories to outline aspects Instead of holding SPEC-variable dependent files and directories inline within the repository structure, move them into 'spec' subdirectories at the corresponding levels, e.g.: repos/base/include/spec repos/base/mk/spec repos/base/lib/mk/spec repos/base/src/core/spec ... Moreover, this commit removes the 'platform' directories. That term was used in an overloaded sense. All SPEC-relative 'platform' directories are now named 'spec'. Other files, like for instance those related to the kernel/architecture specific startup library, where moved from 'platform' directories to explicit, more meaningful places like e.g.: 'src/lib/startup'. Fix #1673
2015-09-03 12:55:05 +00:00
#ifndef _INCLUDE__SPEC__IMX6__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__SPEC__IMX6__DRIVERS__BOARD_BASE_H_
hw: support Wandboard Quad (i.MX6) The port uses the Cortex-A9 private timer for the kernel and an EPIT as user timer. It was successfully tested on the Wandboard Quad and the CuBox-i with the signal test. It lacks L2-cache and Trustzone support by now. Thanks to Praveen Srinivas (IIT Madras, India) and Nikolay Golikov (Ksys Labs LLC, Russia). This work is partially based on their contributions. Fix #1467
2015-03-25 18:30:37 +00:00
namespace Genode
{
/**
* i.MX6 motherboard
*/
struct Board_base;
}
struct Genode::Board_base
{
enum {
/* normal RAM */
RAM0_BASE = 0x10000000,
RAM0_SIZE = 0x80000000,
/* device IO memory */
MMIO_BASE = 0x00000000,
MMIO_SIZE = 0x10000000,
UART_1_IRQ = 58,
UART_1_MMIO_BASE = 0x02020000,
UART_1_MMIO_SIZE = 0x00004000,
/* timer */
EPIT_2_IRQ = 89,
EPIT_2_MMIO_BASE = 0x020d4000,
EPIT_2_MMIO_SIZE = 0x00004000,
/* ARM IP Bus control */
AIPS_1_MMIO_BASE = 0x0207c000,
AIPS_1_MMIO_SIZE = 0x00004000,
AIPS_2_MMIO_BASE = 0x0217c000,
AIPS_2_MMIO_SIZE = 0x00004000,
/* CPU */
CORTEX_A9_PRIVATE_MEM_BASE = 0x00a00000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
CORTEX_A9_PRIVATE_TIMER_CLK = 395037500,
hw: use kernel timer for timer driver * Adds public timeout syscalls to kernel API * Kernel::timeout installs a timeout and binds a signal context to it that shall trigger once the timeout expired * With Kernel::timeout_max_us, one can get the maximum installable timeout * Kernel::timeout_age_us returns the time that has passed since the calling threads last timeout installation * Removes all device specific back-ends for the base-hw timer driver and implements a generic back-end taht uses the kernel timeout API * Adds assertions about the kernel timer frequency that originate from the requirements of the the kernel timeout API and adjusts all timers accordingly by using the their internal dividers * Introduces the Kernel::Clock class. As member of each Kernel::Cpu object it combines the management of the timer of the CPU with a timeout scheduler. Not only the timeout API uses the timeout scheduler but also the CPUs job scheduler for installing scheduling timeouts. * Introduces the Kernel::time_t type for timer tic values and values inherited from timer tics (like microseconds). Fixes #1972
2016-05-18 10:20:04 +00:00
CORTEX_A9_PRIVATE_TIMER_DIV = 170,
hw: support Wandboard Quad (i.MX6) The port uses the Cortex-A9 private timer for the kernel and an EPIT as user timer. It was successfully tested on the Wandboard Quad and the CuBox-i with the signal test. It lacks L2-cache and Trustzone support by now. Thanks to Praveen Srinivas (IIT Madras, India) and Nikolay Golikov (Ksys Labs LLC, Russia). This work is partially based on their contributions. Fix #1467
2015-03-25 18:30:37 +00:00
hw: enable SMP for ARM Cortex A9 This commit enables multi-processing for all Cortex A9 SoCs we currently support. Moreover, it thereby enables the L2 cache for i.MX6 that was not enabled until now. However, the QEMU variants hw_pbxa9 and hw_zynq still only use 1 core, because the busy cpu synchronization used when initializing multiple Cortex A9 cores leads to horrible boot times on QEMU. During this work the CPU initialization in general was reworked. From now on lots of hardware specifics were put into the 'spec' specific files, some generic hook functions and abstractions thereby were eliminated. This results to more lean implementations for instance on non-SMP platforms, or in the x86 case where cache maintainance is a non-issue. Due to the fact that memory/cache coherency and SMP are closely coupled on ARM Cortex A9 this commit combines so different aspects. Fix #1312 Fix #1807
2016-01-11 10:02:52 +00:00
/* L2 cache controller */
PL310_MMIO_BASE = 0x00a02000,
PL310_MMIO_SIZE = 0x00001000,
hw: support Wandboard Quad (i.MX6) The port uses the Cortex-A9 private timer for the kernel and an EPIT as user timer. It was successfully tested on the Wandboard Quad and the CuBox-i with the signal test. It lacks L2-cache and Trustzone support by now. Thanks to Praveen Srinivas (IIT Madras, India) and Nikolay Golikov (Ksys Labs LLC, Russia). This work is partially based on their contributions. Fix #1467
2015-03-25 18:30:37 +00:00
/* CPU cache */
CACHE_LINE_SIZE_LOG2 = 5,
/* wether board provides ARM security extension */
SECURITY_EXTENSION = 1,
};
};
Introduce 'spec' subdirectories to outline aspects Instead of holding SPEC-variable dependent files and directories inline within the repository structure, move them into 'spec' subdirectories at the corresponding levels, e.g.: repos/base/include/spec repos/base/mk/spec repos/base/lib/mk/spec repos/base/src/core/spec ... Moreover, this commit removes the 'platform' directories. That term was used in an overloaded sense. All SPEC-relative 'platform' directories are now named 'spec'. Other files, like for instance those related to the kernel/architecture specific startup library, where moved from 'platform' directories to explicit, more meaningful places like e.g.: 'src/lib/startup'. Fix #1673
2015-09-03 12:55:05 +00:00
#endif /* _INCLUDE__SPEC__IMX6__DRIVERS__BOARD_BASE_H_ */
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