genode/repos/base-hw/mk/spec/hw_riscv.mk

SPECS += hw riscv platform_riscv 64bit

LD_TEXT_ADDR      ?= 0x1000
CORE_LD_TEXT_ADDR  = 0x200
NR_OF_CPUS         = 1
REP_INC_DIR       += include/spec/riscv

include $(call select_from_repositories,mk/spec/64bit.mk)
include $(call select_from_repositories,mk/spec/hw.mk)
base-hw: initial RISC-V support using the spike instruction emulator issue #1880 2016-02-11 10:59:31 +00:00			`SPECS += hw riscv platform_riscv 64bit`

			`LD_TEXT_ADDR ?= 0x1000`
			`CORE_LD_TEXT_ADDR = 0x200`
base-hw: RISC-V Rocket Core on Zynq This commit adds rocket core on the Zynq FPGA support to base HW. It also takes advantage of the new timer infrastructure introduced with the privileged 1.8 and adds improved TLB flush support. fixes #1880 2015-11-10 11:49:05 +00:00			`NR_OF_CPUS = 1`
			`REP_INC_DIR += include/spec/riscv`
base-hw: initial RISC-V support using the spike instruction emulator issue #1880 2016-02-11 10:59:31 +00:00
			`include $(call select_from_repositories,mk/spec/64bit.mk)`
			`include $(call select_from_repositories,mk/spec/hw.mk)`