/* AUTOMATICALLY GENERATED by gen_table_fourcc.py. You should modify
   that script instead of adding here entries manually! */
static const struct drmFormatModifierInfo drm_format_modifier_table[] = {
    { DRM_MODIFIER_INVALID(NONE, INVALID) },
    { DRM_MODIFIER_LINEAR(NONE, LINEAR) },
    { DRM_MODIFIER_INTEL(X_TILED, X_TILED) },
    { DRM_MODIFIER_INTEL(Y_TILED, Y_TILED) },
    { DRM_MODIFIER_INTEL(Yf_TILED, Yf_TILED) },
    { DRM_MODIFIER_INTEL(Y_TILED_CCS, Y_TILED_CCS) },
    { DRM_MODIFIER_INTEL(Yf_TILED_CCS, Yf_TILED_CCS) },
    { DRM_MODIFIER_INTEL(Y_TILED_GEN12_RC_CCS, Y_TILED_GEN12_RC_CCS) },
    { DRM_MODIFIER_INTEL(Y_TILED_GEN12_MC_CCS, Y_TILED_GEN12_MC_CCS) },
    { DRM_MODIFIER_INTEL(Y_TILED_GEN12_RC_CCS_CC, Y_TILED_GEN12_RC_CCS_CC) },
    { DRM_MODIFIER_INTEL(4_TILED, 4_TILED) },
    { DRM_MODIFIER_INTEL(4_TILED_DG2_RC_CCS, 4_TILED_DG2_RC_CCS) },
    { DRM_MODIFIER_INTEL(4_TILED_DG2_MC_CCS, 4_TILED_DG2_MC_CCS) },
    { DRM_MODIFIER_INTEL(4_TILED_DG2_RC_CCS_CC, 4_TILED_DG2_RC_CCS_CC) },
    { DRM_MODIFIER_INTEL(4_TILED_MTL_RC_CCS, 4_TILED_MTL_RC_CCS) },
    { DRM_MODIFIER_INTEL(4_TILED_MTL_MC_CCS, 4_TILED_MTL_MC_CCS) },
    { DRM_MODIFIER_INTEL(4_TILED_MTL_RC_CCS_CC, 4_TILED_MTL_RC_CCS_CC) },
    { DRM_MODIFIER(SAMSUNG, 64_32_TILE, 64_32_TILE) },
    { DRM_MODIFIER(SAMSUNG, 16_16_TILE, 16_16_TILE) },
    { DRM_MODIFIER(QCOM, COMPRESSED, COMPRESSED) },
    { DRM_MODIFIER(QCOM, TILED3, TILED3) },
    { DRM_MODIFIER(QCOM, TILED2, TILED2) },
    { DRM_MODIFIER(VIVANTE, TILED, TILED) },
    { DRM_MODIFIER(VIVANTE, SUPER_TILED, SUPER_TILED) },
    { DRM_MODIFIER(VIVANTE, SPLIT_TILED, SPLIT_TILED) },
    { DRM_MODIFIER(VIVANTE, SPLIT_SUPER_TILED, SPLIT_SUPER_TILED) },
    { DRM_MODIFIER(NVIDIA, TEGRA_TILED, TEGRA_TILED) },
    { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_ONE_GOB, 16BX2_BLOCK_ONE_GOB) },
    { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_TWO_GOB, 16BX2_BLOCK_TWO_GOB) },
    { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_FOUR_GOB, 16BX2_BLOCK_FOUR_GOB) },
    { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_EIGHT_GOB, 16BX2_BLOCK_EIGHT_GOB) },
    { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_SIXTEEN_GOB, 16BX2_BLOCK_SIXTEEN_GOB) },
    { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_THIRTYTWO_GOB, 16BX2_BLOCK_THIRTYTWO_GOB) },
    { DRM_MODIFIER(BROADCOM, VC4_T_TILED, VC4_T_TILED) },
    { DRM_MODIFIER(BROADCOM, SAND32, SAND32) },
    { DRM_MODIFIER(BROADCOM, SAND64, SAND64) },
    { DRM_MODIFIER(BROADCOM, SAND128, SAND128) },
    { DRM_MODIFIER(BROADCOM, SAND256, SAND256) },
    { DRM_MODIFIER(BROADCOM, UIF, UIF) },
    { DRM_MODIFIER(ARM, 16X16_BLOCK_U_INTERLEAVED, 16X16_BLOCK_U_INTERLEAVED) },
    { DRM_MODIFIER(ALLWINNER, TILED, TILED) },
};
static const struct drmFormatModifierVendorInfo drm_format_modifier_vendor_table[] = {
    { DRM_FORMAT_MOD_VENDOR_NONE, "NONE" },
    { DRM_FORMAT_MOD_VENDOR_INTEL, "INTEL" },
    { DRM_FORMAT_MOD_VENDOR_AMD, "AMD" },
    { DRM_FORMAT_MOD_VENDOR_NVIDIA, "NVIDIA" },
    { DRM_FORMAT_MOD_VENDOR_SAMSUNG, "SAMSUNG" },
    { DRM_FORMAT_MOD_VENDOR_QCOM, "QCOM" },
    { DRM_FORMAT_MOD_VENDOR_VIVANTE, "VIVANTE" },
    { DRM_FORMAT_MOD_VENDOR_BROADCOM, "BROADCOM" },
    { DRM_FORMAT_MOD_VENDOR_ARM, "ARM" },
    { DRM_FORMAT_MOD_VENDOR_ALLWINNER, "ALLWINNER" },
    { DRM_FORMAT_MOD_VENDOR_AMLOGIC, "AMLOGIC" },
};
