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Add gcc 11.4.0 and regenerate patches against the new version. https://gcc.gnu.org/pipermail/gcc-announce/2023/000177.html https://gcc.gnu.org/gcc-11/changes.html Signed-off-by: Chris Packham <judge.packham@gmail.com>
127 lines
3.6 KiB
Diff
127 lines
3.6 KiB
Diff
From e73e3c3eaf2c3ea45083dda5dc4b7d29f6a03238 Mon Sep 17 00:00:00 2001
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From: Claudiu Zissulescu <claziss@synopsys.com>
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Date: Wed, 6 Oct 2021 09:47:50 +0300
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Subject: [PATCH] arc: Fix maddhisi patterns
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See for more details: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues/429
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---
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gcc/config/arc/arc.md | 43 +++++++---------------------------
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gcc/testsuite/gcc.target/arc/tmac-4.c | 29 ++++++++++++++++++++++
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2 files changed, 39 insertions(+), 33 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/arc/tmac-4.c
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--- a/gcc/config/arc/arc.md
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+++ b/gcc/config/arc/arc.md
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@@ -6055,33 +6055,22 @@
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(match_operand:SI 3 "register_operand" "")]
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"TARGET_PLUS_MACD"
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"{
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- rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
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+ rtx acc_reg = gen_rtx_REG (SImode, ACCL_REGNO);
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emit_move_insn (acc_reg, operands[3]);
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- emit_insn (gen_machi (operands[0], operands[1], operands[2]));
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+ emit_insn (gen_machi (operands[0], operands[1], operands[2], acc_reg));
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DONE;
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}")
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-(define_insn_and_split "machi"
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+(define_insn "machi"
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[(set (match_operand:SI 0 "register_operand" "=Ral,r")
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(plus:SI
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(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r,r"))
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(sign_extend:SI (match_operand:HI 2 "register_operand" "r,r")))
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- (reg:SI ARCV2_ACC)))
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+ (match_operand:SI 3 "accl_operand" "")))
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(clobber (reg:DI ARCV2_ACC))]
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"TARGET_PLUS_MACD"
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- "@
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- vmac2h\\t%0,%1,%2
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- #"
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- "&& reload_completed && (REGNO (operands[0]) != ACCL_REGNO)"
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- [(parallel
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- [(set (reg:SI ARCV2_ACC)
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- (plus:SI (mult:SI (sign_extend:SI (match_dup 1))
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- (sign_extend:SI (match_dup 2)))
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- (reg:SI ARCV2_ACC)))
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- (clobber (reg:DI ARCV2_ACC))])
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- (set (match_dup 0) (reg:SI ARCV2_ACC))]
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- ""
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+ "dmach\\t%0,%1,%2"
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[(set_attr "length" "4")
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(set_attr "type" "multi")
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(set_attr "predicable" "no")
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@@ -6095,34 +6084,22 @@
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(match_operand:SI 3 "register_operand" "")]
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"TARGET_PLUS_MACD"
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"{
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- rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
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+ rtx acc_reg = gen_rtx_REG (SImode, ACCL_REGNO);
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emit_move_insn (acc_reg, operands[3]);
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- emit_insn (gen_umachi (operands[0], operands[1], operands[2]));
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+ emit_insn (gen_umachi (operands[0], operands[1], operands[2], acc_reg));
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DONE;
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}")
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-
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-(define_insn_and_split "umachi"
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+(define_insn "umachi"
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[(set (match_operand:SI 0 "register_operand" "=Ral,r")
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(plus:SI
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(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r,r"))
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(zero_extend:SI (match_operand:HI 2 "register_operand" "r,r")))
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- (reg:SI ARCV2_ACC)))
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+ (match_operand:SI 3 "accl_operand" "")))
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(clobber (reg:DI ARCV2_ACC))]
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"TARGET_PLUS_MACD"
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- "@
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- vmac2hu\\t%0,%1,%2
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- #"
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- "&& reload_completed && (REGNO (operands[0]) != ACCL_REGNO)"
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- [(parallel
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- [(set (reg:SI ARCV2_ACC)
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- (plus:SI (mult:SI (zero_extend:SI (match_dup 1))
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- (zero_extend:SI (match_dup 2)))
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- (reg:SI ARCV2_ACC)))
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- (clobber (reg:DI ARCV2_ACC))])
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- (set (match_dup 0) (reg:SI ARCV2_ACC))]
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- ""
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+ "dmachu\\t%0,%1,%2"
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[(set_attr "length" "4")
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(set_attr "type" "multi")
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(set_attr "predicable" "no")
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/arc/tmac-4.c
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@@ -0,0 +1,29 @@
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+/* { dg-do compile } */
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+/* { dg-skip-if "" { ! { clmcpu } } } */
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+/* { dg-options "-O3 -mbig-endian -mcpu=hs38" } */
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+
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+struct a {};
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+struct b {
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+ int c;
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+ int d;
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+};
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+
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+struct {
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+ struct a e;
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+ struct b f[];
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+} g;
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+short h;
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+
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+extern void bar (int *);
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+
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+int foo(void)
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+{
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+ struct b *a;
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+ for (;;)
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+ {
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+ a = &g.f[h];
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+ bar(&a->d);
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+ }
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+}
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+
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+/* { dg-final { scan-assembler "dmach" } } */
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