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The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core. Processor and SOC vendors can select from various processor options and even create customized instructions in addition to a base ISA to tailor the processor for a particular application. Because of the configurability, the build process requires one additional step for gcc, binutils, and gdb to update the default configuration. These configurations are packed into an 'overlay' tar image, and are simply untarred on top of the default configuration during the build. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> |
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| .. | ||
| alpha.in | ||
| alpha.in.2 | ||
| arm.in | ||
| arm.in.2 | ||
| avr.in | ||
| m68k.in | ||
| microblaze.in | ||
| mips.in | ||
| mips.in.2 | ||
| nios2.in | ||
| powerpc.in | ||
| powerpc.in.2 | ||
| s390.in | ||
| sh.in | ||
| sh.in.2 | ||
| sparc.in | ||
| x86.in | ||
| xtensa.in | ||
| xtensa.in.2 | ||