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c175b21ce4
Bring in the fixes for GCC 7 through 13. https://rtx.meta.security/mitigation/2023/09/12/CVE-2023-4039.html https://developer.arm.com/Arm%20Security%20Center/GCC%20Stack%20Protector%20Vulnerability%20AArch64 Signed-off-by: Chris Packham <judge.packham@gmail.com>
222 lines
9.4 KiB
Diff
222 lines
9.4 KiB
Diff
From 6ef2e97b16bea4d4ce2cd52de444a3a2595504d6 Mon Sep 17 00:00:00 2001
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From: Richard Sandiford <richard.sandiford@arm.com>
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Date: Tue, 27 Jun 2023 11:21:41 +0100
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Subject: [PATCH 29/42] aarch64: Tweak aarch64_save/restore_callee_saves
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aarch64_save_callee_saves and aarch64_restore_callee_saves took
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a parameter called start_offset that gives the offset of the
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bottom of the saved register area from the current stack pointer.
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However, it's more convenient for later patches if we use the
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bottom of the entire frame as the reference point, rather than
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the bottom of the saved registers.
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Doing that removes the need for the callee_offset field.
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Other than that, this is not a win on its own. It only really
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makes sense in combination with the follow-on patches.
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gcc/
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* config/aarch64/aarch64.h (aarch64_frame::callee_offset): Delete.
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* config/aarch64/aarch64.c (aarch64_layout_frame): Remove
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callee_offset handling.
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(aarch64_save_callee_saves): Replace the start_offset parameter
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with a bytes_below_sp parameter.
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(aarch64_restore_callee_saves): Likewise.
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(aarch64_expand_prologue): Update accordingly.
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(aarch64_expand_epilogue): Likewise.
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---
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gcc/config/aarch64/aarch64.c | 56 ++++++++++++++++++------------------
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gcc/config/aarch64/aarch64.h | 4 ---
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2 files changed, 28 insertions(+), 32 deletions(-)
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diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
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index 2652515b3615..884002e3b7b5 100644
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--- a/gcc/config/aarch64/aarch64.c
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+++ b/gcc/config/aarch64/aarch64.c
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@@ -7028,7 +7028,6 @@ aarch64_layout_frame (void)
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frame.final_adjust = 0;
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frame.callee_adjust = 0;
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frame.sve_callee_adjust = 0;
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- frame.callee_offset = 0;
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HOST_WIDE_INT max_push_offset = 0;
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if (frame.wb_candidate2 != INVALID_REGNUM)
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@@ -7068,7 +7067,6 @@ aarch64_layout_frame (void)
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stp reg1, reg2, [sp, bytes_below_saved_regs]
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stp reg3, reg4, [sp, bytes_below_saved_regs + 16] */
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frame.initial_adjust = frame.frame_size;
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- frame.callee_offset = const_below_saved_regs;
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}
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else if (saves_below_hard_fp_p
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&& known_eq (frame.saved_regs_size,
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@@ -7398,12 +7396,13 @@ aarch64_add_cfa_expression (rtx_insn *insn, rtx reg,
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}
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/* Emit code to save the callee-saved registers from register number START
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- to LIMIT to the stack at the location starting at offset START_OFFSET,
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- skipping any write-back candidates if SKIP_WB is true. HARD_FP_VALID_P
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- is true if the hard frame pointer has been set up. */
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+ to LIMIT to the stack. The stack pointer is currently BYTES_BELOW_SP
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+ bytes above the bottom of the static frame. Skip any write-back
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+ candidates if SKIP_WB is true. HARD_FP_VALID_P is true if the hard
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+ frame pointer has been set up. */
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static void
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-aarch64_save_callee_saves (poly_int64 start_offset,
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+aarch64_save_callee_saves (poly_int64 bytes_below_sp,
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unsigned start, unsigned limit, bool skip_wb,
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bool hard_fp_valid_p)
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{
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@@ -7431,7 +7430,9 @@ aarch64_save_callee_saves (poly_int64 start_offset,
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machine_mode mode = aarch64_reg_save_mode (regno);
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reg = gen_rtx_REG (mode, regno);
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- offset = start_offset + frame.reg_offset[regno];
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+ offset = (frame.reg_offset[regno]
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+ + frame.bytes_below_saved_regs
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+ - bytes_below_sp);
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rtx base_rtx = stack_pointer_rtx;
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poly_int64 sp_offset = offset;
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@@ -7442,9 +7443,7 @@ aarch64_save_callee_saves (poly_int64 start_offset,
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else if (GP_REGNUM_P (regno)
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&& (!offset.is_constant (&const_offset) || const_offset >= 512))
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{
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- gcc_assert (known_eq (start_offset, 0));
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- poly_int64 fp_offset
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- = frame.below_hard_fp_saved_regs_size;
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+ poly_int64 fp_offset = frame.bytes_below_hard_fp - bytes_below_sp;
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if (hard_fp_valid_p)
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base_rtx = hard_frame_pointer_rtx;
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else
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@@ -7508,12 +7507,13 @@ aarch64_save_callee_saves (poly_int64 start_offset,
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}
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/* Emit code to restore the callee registers from register number START
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- up to and including LIMIT. Restore from the stack offset START_OFFSET,
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- skipping any write-back candidates if SKIP_WB is true. Write the
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- appropriate REG_CFA_RESTORE notes into CFI_OPS. */
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+ up to and including LIMIT. The stack pointer is currently BYTES_BELOW_SP
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+ bytes above the bottom of the static frame. Skip any write-back
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+ candidates if SKIP_WB is true. Write the appropriate REG_CFA_RESTORE
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+ notes into CFI_OPS. */
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static void
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-aarch64_restore_callee_saves (poly_int64 start_offset, unsigned start,
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+aarch64_restore_callee_saves (poly_int64 bytes_below_sp, unsigned start,
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unsigned limit, bool skip_wb, rtx *cfi_ops)
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{
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aarch64_frame &frame = cfun->machine->frame;
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@@ -7539,7 +7539,9 @@ aarch64_restore_callee_saves (poly_int64 start_offset, unsigned start,
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machine_mode mode = aarch64_reg_save_mode (regno);
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reg = gen_rtx_REG (mode, regno);
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- offset = start_offset + frame.reg_offset[regno];
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+ offset = (frame.reg_offset[regno]
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+ + frame.bytes_below_saved_regs
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+ - bytes_below_sp);
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rtx base_rtx = stack_pointer_rtx;
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if (mode == VNx2DImode && BYTES_BIG_ENDIAN)
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aarch64_adjust_sve_callee_save_base (mode, base_rtx, anchor_reg,
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@@ -8304,8 +8306,6 @@ aarch64_expand_prologue (void)
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HOST_WIDE_INT callee_adjust = frame.callee_adjust;
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poly_int64 final_adjust = frame.final_adjust;
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poly_int64 sve_callee_adjust = frame.sve_callee_adjust;
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- poly_int64 below_hard_fp_saved_regs_size
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- = frame.below_hard_fp_saved_regs_size;
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unsigned reg1 = frame.wb_candidate1;
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unsigned reg2 = frame.wb_candidate2;
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bool emit_frame_chain = frame.emit_frame_chain;
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@@ -8377,8 +8377,8 @@ aarch64_expand_prologue (void)
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- frame.hard_fp_offset);
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gcc_assert (known_ge (chain_offset, 0));
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- /* The offset of the bottom of the save area from the current SP. */
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- poly_int64 saved_regs_offset = chain_offset - below_hard_fp_saved_regs_size;
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+ /* The offset of the current SP from the bottom of the static frame. */
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+ poly_int64 bytes_below_sp = frame_size - initial_adjust - callee_adjust;
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if (emit_frame_chain)
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{
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@@ -8386,7 +8386,7 @@ aarch64_expand_prologue (void)
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{
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reg1 = R29_REGNUM;
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reg2 = R30_REGNUM;
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- aarch64_save_callee_saves (saved_regs_offset, reg1, reg2,
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+ aarch64_save_callee_saves (bytes_below_sp, reg1, reg2,
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false, false);
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}
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else
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@@ -8426,7 +8426,7 @@ aarch64_expand_prologue (void)
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emit_insn (gen_stack_tie (stack_pointer_rtx, hard_frame_pointer_rtx));
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}
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- aarch64_save_callee_saves (saved_regs_offset, R0_REGNUM, R30_REGNUM,
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+ aarch64_save_callee_saves (bytes_below_sp, R0_REGNUM, R30_REGNUM,
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callee_adjust != 0 || emit_frame_chain,
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emit_frame_chain);
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if (maybe_ne (sve_callee_adjust, 0))
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@@ -8436,16 +8436,17 @@ aarch64_expand_prologue (void)
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aarch64_allocate_and_probe_stack_space (tmp1_rtx, tmp0_rtx,
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sve_callee_adjust,
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!frame_pointer_needed, false);
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- saved_regs_offset += sve_callee_adjust;
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+ bytes_below_sp -= sve_callee_adjust;
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}
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- aarch64_save_callee_saves (saved_regs_offset, P0_REGNUM, P15_REGNUM,
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+ aarch64_save_callee_saves (bytes_below_sp, P0_REGNUM, P15_REGNUM,
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false, emit_frame_chain);
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- aarch64_save_callee_saves (saved_regs_offset, V0_REGNUM, V31_REGNUM,
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+ aarch64_save_callee_saves (bytes_below_sp, V0_REGNUM, V31_REGNUM,
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callee_adjust != 0 || emit_frame_chain,
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emit_frame_chain);
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/* We may need to probe the final adjustment if it is larger than the guard
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that is assumed by the called. */
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+ gcc_assert (known_eq (bytes_below_sp, final_adjust));
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aarch64_allocate_and_probe_stack_space (tmp1_rtx, tmp0_rtx, final_adjust,
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!frame_pointer_needed, true);
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}
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@@ -8480,7 +8481,6 @@ aarch64_expand_epilogue (bool for_sibcall)
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poly_int64 initial_adjust = frame.initial_adjust;
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HOST_WIDE_INT callee_adjust = frame.callee_adjust;
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poly_int64 final_adjust = frame.final_adjust;
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- poly_int64 callee_offset = frame.callee_offset;
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poly_int64 sve_callee_adjust = frame.sve_callee_adjust;
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poly_int64 bytes_below_hard_fp = frame.bytes_below_hard_fp;
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unsigned reg1 = frame.wb_candidate1;
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@@ -8548,13 +8548,13 @@ aarch64_expand_epilogue (bool for_sibcall)
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/* Restore the vector registers before the predicate registers,
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so that we can use P4 as a temporary for big-endian SVE frames. */
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- aarch64_restore_callee_saves (callee_offset, V0_REGNUM, V31_REGNUM,
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+ aarch64_restore_callee_saves (final_adjust, V0_REGNUM, V31_REGNUM,
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callee_adjust != 0, &cfi_ops);
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- aarch64_restore_callee_saves (callee_offset, P0_REGNUM, P15_REGNUM,
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+ aarch64_restore_callee_saves (final_adjust, P0_REGNUM, P15_REGNUM,
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false, &cfi_ops);
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if (maybe_ne (sve_callee_adjust, 0))
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aarch64_add_sp (NULL_RTX, NULL_RTX, sve_callee_adjust, true);
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- aarch64_restore_callee_saves (callee_offset - sve_callee_adjust,
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+ aarch64_restore_callee_saves (final_adjust + sve_callee_adjust,
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R0_REGNUM, R30_REGNUM,
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callee_adjust != 0, &cfi_ops);
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diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
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index a4cbc678cef3..405b7545913d 100644
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--- a/gcc/config/aarch64/aarch64.h
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+++ b/gcc/config/aarch64/aarch64.h
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@@ -856,10 +856,6 @@ struct GTY (()) aarch64_frame
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It is zero when no push is used. */
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HOST_WIDE_INT callee_adjust;
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- /* The offset from SP to the callee-save registers after initial_adjust.
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- It may be non-zero if no push is used (ie. callee_adjust == 0). */
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- poly_int64 callee_offset;
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-
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/* The size of the stack adjustment before saving or after restoring
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SVE registers. */
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poly_int64 sve_callee_adjust;
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--
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2.42.0
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