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The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core. Processor and SOC vendors can select from various processor options and even create customized instructions in addition to a base ISA to tailor the processor for a particular application. Because of the configurability, the build process requires one additional step for gcc, binutils, and gdb to update the default configuration. These configurations are packed into an 'overlay' tar image, and are simply untarred on top of the default configuration during the build. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
31 lines
914 B
Groff
31 lines
914 B
Groff
choice
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prompt "Target Architecture Variant"
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default ARCH_xtensa_fsf
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config XTENSA_CUSTOM
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bool "Custom Xtensa processor configuration"
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config ARCH_xtensa_fsf
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bool "fsf - Default configuration"
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endchoice
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config ARCH_XTENSA_CUSTOM_NAME
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string "Custom Xtensa process configuration file name"
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depends on XTENSA_CUSTOM
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default ""
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help
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Enter the name of the custom processor configuration
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overlay file or leave blank to use the default 'xtensa-overlay.tar'.
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For more information about this option, please also consult
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the 'help' section of the 'Target Architecture Variant'
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option above.
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config ARCH_XTENSA_CUSTOM_OVERLAY_LOCATION
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string "Full path to custom Xtensa processor configurations"
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depends on XTENSA_CUSTOM
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default ""
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help
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Enter the path to the directory for the custom processor
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configuration file or leave blank to use the default location:
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CT_CUSTOM_LOCATION_ROOT_DIR
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