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https://gcc.gnu.org/pipermail/gcc-announce/2024/000183.html Add the new version drop the patches that have been applied upstream. Signed-off-by: Chris Packham <judge.packham@gmail.com>
116 lines
3.9 KiB
Diff
116 lines
3.9 KiB
Diff
From f62aee446c2fa01016db09541d381f13b4fd08fa Mon Sep 17 00:00:00 2001
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From: Claudiu Zissulescu <claziss@synopsys.com>
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Date: Thu, 30 Sep 2021 14:08:39 +0300
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Subject: [PATCH] arc: Update (u)maddhisi4 patterns
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The (u)maddsihi4 patterns are using the ARC's VMAC2H(U)
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instruction with null destination, however, VMAC2H(U) doesn't
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rewrite the accumulator. This patch solves the destination issue
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of VMAC2H by using the accumulator, and is using a
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define_insn_and_split to generate the extra move from the
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accumulator to the destination register.
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gcc/
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* config/arc/arc.md (maddhisi4): Use a single move to accumulator.
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(umaddhisi4): Likewise.
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(machi): Convert it to an define_insn_and_split pattern.
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(umachi): Likewise.
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See for more details: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues/427
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Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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---
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gcc/config/arc/arc.md | 57 +++++++++++++++++++++++++++++++++++---------------
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1 file changed, 40 insertions(+), 17 deletions(-)
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--- a/gcc/config/arc/arc.md
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+++ b/gcc/config/arc/arc.md
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@@ -6051,26 +6051,37 @@
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(define_expand "maddhisi4"
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[(match_operand:SI 0 "register_operand" "")
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(match_operand:HI 1 "register_operand" "")
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- (match_operand:HI 2 "extend_operand" "")
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+ (match_operand:HI 2 "register_operand" "")
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(match_operand:SI 3 "register_operand" "")]
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"TARGET_PLUS_MACD"
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"{
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rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
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emit_move_insn (acc_reg, operands[3]);
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- emit_insn (gen_machi (operands[1], operands[2]));
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- emit_move_insn (operands[0], acc_reg);
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+ emit_insn (gen_machi (operands[0], operands[1], operands[2]));
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DONE;
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}")
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-(define_insn "machi"
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- [(set (reg:SI ARCV2_ACC)
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+(define_insn_and_split "machi"
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+ [(set (match_operand:SI 0 "register_operand" "=Ral,r")
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(plus:SI
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- (mult:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "%r"))
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- (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))
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- (reg:SI ARCV2_ACC)))]
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+ (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r,r"))
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+ (sign_extend:SI (match_operand:HI 2 "register_operand" "r,r")))
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+ (reg:SI ARCV2_ACC)))
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+ (clobber (reg:DI ARCV2_ACC))]
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"TARGET_PLUS_MACD"
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- "vmac2h\\t0,%0,%1"
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+ "@
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+ vmac2h\\t%0,%1,%2
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+ #"
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+ "&& reload_completed && (REGNO (operands[0]) != ACCL_REGNO)"
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+ [(parallel
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+ [(set (reg:SI ARCV2_ACC)
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+ (plus:SI (mult:SI (sign_extend:SI (match_dup 1))
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+ (sign_extend:SI (match_dup 2)))
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+ (reg:SI ARCV2_ACC)))
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+ (clobber (reg:DI ARCV2_ACC))])
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+ (set (match_dup 0) (reg:SI ARCV2_ACC))]
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+ ""
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[(set_attr "length" "4")
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(set_attr "type" "multi")
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(set_attr "predicable" "no")
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@@ -6087,19 +6098,31 @@
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rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
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emit_move_insn (acc_reg, operands[3]);
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- emit_insn (gen_umachi (operands[1], operands[2]));
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- emit_move_insn (operands[0], acc_reg);
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+ emit_insn (gen_umachi (operands[0], operands[1], operands[2]));
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DONE;
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}")
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-(define_insn "umachi"
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- [(set (reg:SI ARCV2_ACC)
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+
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+(define_insn_and_split "umachi"
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+ [(set (match_operand:SI 0 "register_operand" "=Ral,r")
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(plus:SI
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- (mult:SI (zero_extend:SI (match_operand:HI 0 "register_operand" "%r"))
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- (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
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- (reg:SI ARCV2_ACC)))]
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+ (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r,r"))
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+ (zero_extend:SI (match_operand:HI 2 "register_operand" "r,r")))
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+ (reg:SI ARCV2_ACC)))
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+ (clobber (reg:DI ARCV2_ACC))]
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"TARGET_PLUS_MACD"
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- "vmac2hu\\t0,%0,%1"
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+ "@
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+ vmac2hu\\t%0,%1,%2
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+ #"
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+ "&& reload_completed && (REGNO (operands[0]) != ACCL_REGNO)"
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+ [(parallel
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+ [(set (reg:SI ARCV2_ACC)
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+ (plus:SI (mult:SI (zero_extend:SI (match_dup 1))
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+ (zero_extend:SI (match_dup 2)))
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+ (reg:SI ARCV2_ACC)))
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+ (clobber (reg:DI ARCV2_ACC))])
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+ (set (match_dup 0) (reg:SI ARCV2_ACC))]
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+ ""
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[(set_attr "length" "4")
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(set_attr "type" "multi")
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(set_attr "predicable" "no")
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