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http://sourceware.org/ml/crossgcc/2008-10/msg00067.html /trunk/patches/glibc/2.7/290-powerpc-8xx-CPU15-errata.patch | 40 40 0 0 +++++++++++++++++++ 1 file changed, 40 insertions(+)
41 lines
1.4 KiB
Diff
41 lines
1.4 KiB
Diff
Fix memset on PowerPC 8xx, by Nye Liu:
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http://sourceware.org/ml/crossgcc/2008-10/msg00067.html
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Quote:
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I am working on a powerpc 860 toolchain, but I am having problems
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convincing glibc to not emit code that uses the dcbz instruction (CPU15
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dcbX bug). The source of the problem is sysdeps/powerpc/power3/memset.S
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--- glibc-2.7/sysdeps/powerpc/powerpc32/memset.S 2007-03-26 13:09:07.000000000 -0700
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+++ glibc-2.7/sysdeps/powerpc/powerpc32/memset.S.new 2008-10-23 12:20:04.000000000 -0700
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@@ -112,11 +112,13 @@
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clrrwi. rALIGN, rLEN, 5
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mtcrf 0x01, rLEN /* 40th instruction from .align */
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+#ifndef BROKEN_PPC_8xx_CPU15
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/* Check if we can use the special case for clearing memory using dcbz.
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This requires that we know the correct cache line size for this
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processor. Getting the __cache_line_size may require establishing GOT
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addressability, so branch out of line to set this up. */
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beq cr1, L(checklinesize)
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+#endif
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/* Store blocks of 32-bytes (256-bits) starting on a 32-byte boundary.
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Can't assume that rCHR is zero or that the cache line size is either
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@@ -248,6 +250,7 @@
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stw rCHR, -8(rMEMP)
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blr
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+#ifndef BROKEN_PPC_8xx_CPU15
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L(checklinesize):
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#ifdef SHARED
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mflr rTMP
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@@ -329,6 +332,7 @@
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L(handletail32):
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clrrwi. rALIGN, rLEN, 5
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b L(nondcbz)
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+#endif /* ! BROKEN_PPC_8xx_CPU15 */
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END (BP_SYM (memset))
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libc_hidden_builtin_def (memset)
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