mirror of
https://github.com/crosstool-ng/crosstool-ng.git
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Merge branch 'more-gcc11-fixes-for-arc' of https://github.com/foss-for-synopsys-dwc-arc-processors/crosstool-ng
Signed-off-by: Chris Packham <judge.packham@gmail.com>
This commit is contained in:
Chris Packham
commit
405449624a
44
packages/gcc/11.2.0/0006-arc-Update-ZOL-pattern.patch
vendored
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44
packages/gcc/11.2.0/0006-arc-Update-ZOL-pattern.patch
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@ -0,0 +1,44 @@
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From 7efc628f79a1801b292623dfe5aa8c53a61a2121 Mon Sep 17 00:00:00 2001
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From: Claudiu Zissulescu <claziss@synopsys.com>
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Date: Tue, 14 Sep 2021 12:25:43 +0300
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Subject: [PATCH] arc: Update ZOL pattern.
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The ZOL pattern is missing modes which may lead to errors during
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var_tracking. Add them.
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gcc/
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* config/arc/arc.md (doloop_end): Add missing mode.
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(loop_end): Likewise.
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See more details here: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues/398
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Will be a part of GCC 12, see: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=9bb20299ba1d1cc3bbd83a07a777fcc5a93cfeb0
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Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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---
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gcc/config/arc/arc.md | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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--- a/gcc/config/arc/arc.md
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+++ b/gcc/config/arc/arc.md
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@@ -4990,8 +4990,8 @@
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(const_int 1))
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(label_ref (match_operand 1 "" ""))
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(pc)))
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- (set (match_dup 0) (plus (match_dup 0) (const_int -1)))
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- (unspec [(const_int 0)] UNSPEC_ARC_LP)
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+ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))
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+ (unspec:SI [(const_int 0)] UNSPEC_ARC_LP)
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(clobber (match_dup 2))])]
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""
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{
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@@ -5020,8 +5020,8 @@
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(const_int 1))
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(label_ref (match_operand 1 "" ""))
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(pc)))
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- (set (match_dup 0) (plus (match_dup 0) (const_int -1)))
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- (unspec [(const_int 0)] UNSPEC_ARC_LP)
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+ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))
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+ (unspec:SI [(const_int 0)] UNSPEC_ARC_LP)
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(clobber (match_scratch:SI 2 "=X,&r"))]
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""
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"@
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115
packages/gcc/11.2.0/0007-arc-Update-u-maddhisi4-patterns.patch
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115
packages/gcc/11.2.0/0007-arc-Update-u-maddhisi4-patterns.patch
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From b3873d67e4e8a1f16efbfa6ad7d73b9809bb2dd2 Mon Sep 17 00:00:00 2001
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From: Claudiu Zissulescu <claziss@synopsys.com>
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Date: Thu, 30 Sep 2021 14:08:39 +0300
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Subject: [PATCH] arc: Update (u)maddhisi4 patterns
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The (u)maddsihi4 patterns are using the ARC's VMAC2H(U)
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instruction with null destination, however, VMAC2H(U) doesn't
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rewrite the accumulator. This patch solves the destination issue
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of VMAC2H by using the accumulator, and is using a
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define_insn_and_split to generate the extra move from the
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accumulator to the destination register.
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gcc/
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* config/arc/arc.md (maddhisi4): Use a single move to accumulator.
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(umaddhisi4): Likewise.
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(machi): Convert it to an define_insn_and_split pattern.
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(umachi): Likewise.
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See for more details: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues/427
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Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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---
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gcc/config/arc/arc.md | 57 +++++++++++++++++++++++++++++++++++---------------
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1 file changed, 40 insertions(+), 17 deletions(-)
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--- a/gcc/config/arc/arc.md
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+++ b/gcc/config/arc/arc.md
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@@ -6051,26 +6051,37 @@
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(define_expand "maddhisi4"
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[(match_operand:SI 0 "register_operand" "")
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(match_operand:HI 1 "register_operand" "")
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- (match_operand:HI 2 "extend_operand" "")
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+ (match_operand:HI 2 "register_operand" "")
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(match_operand:SI 3 "register_operand" "")]
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"TARGET_PLUS_MACD"
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"{
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rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
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emit_move_insn (acc_reg, operands[3]);
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- emit_insn (gen_machi (operands[1], operands[2]));
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- emit_move_insn (operands[0], acc_reg);
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+ emit_insn (gen_machi (operands[0], operands[1], operands[2]));
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DONE;
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}")
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-(define_insn "machi"
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- [(set (reg:SI ARCV2_ACC)
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+(define_insn_and_split "machi"
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+ [(set (match_operand:SI 0 "register_operand" "=Ral,r")
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(plus:SI
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- (mult:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "%r"))
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- (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))
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- (reg:SI ARCV2_ACC)))]
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+ (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r,r"))
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+ (sign_extend:SI (match_operand:HI 2 "register_operand" "r,r")))
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+ (reg:SI ARCV2_ACC)))
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+ (clobber (reg:DI ARCV2_ACC))]
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"TARGET_PLUS_MACD"
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- "vmac2h\\t0,%0,%1"
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+ "@
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+ vmac2h\\t%0,%1,%2
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+ #"
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+ "&& reload_completed && (REGNO (operands[0]) != ACCL_REGNO)"
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+ [(parallel
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+ [(set (reg:SI ARCV2_ACC)
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+ (plus:SI (mult:SI (sign_extend:SI (match_dup 1))
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+ (sign_extend:SI (match_dup 2)))
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+ (reg:SI ARCV2_ACC)))
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+ (clobber (reg:DI ARCV2_ACC))])
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+ (set (match_dup 0) (reg:SI ARCV2_ACC))]
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+ ""
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[(set_attr "length" "4")
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(set_attr "type" "multi")
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(set_attr "predicable" "no")
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@@ -6087,19 +6098,31 @@
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rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
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emit_move_insn (acc_reg, operands[3]);
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- emit_insn (gen_umachi (operands[1], operands[2]));
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- emit_move_insn (operands[0], acc_reg);
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+ emit_insn (gen_umachi (operands[0], operands[1], operands[2]));
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DONE;
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}")
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-(define_insn "umachi"
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- [(set (reg:SI ARCV2_ACC)
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+
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+(define_insn_and_split "umachi"
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+ [(set (match_operand:SI 0 "register_operand" "=Ral,r")
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(plus:SI
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- (mult:SI (zero_extend:SI (match_operand:HI 0 "register_operand" "%r"))
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- (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
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- (reg:SI ARCV2_ACC)))]
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+ (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r,r"))
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+ (zero_extend:SI (match_operand:HI 2 "register_operand" "r,r")))
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+ (reg:SI ARCV2_ACC)))
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+ (clobber (reg:DI ARCV2_ACC))]
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"TARGET_PLUS_MACD"
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- "vmac2hu\\t0,%0,%1"
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+ "@
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+ vmac2hu\\t%0,%1,%2
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+ #"
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+ "&& reload_completed && (REGNO (operands[0]) != ACCL_REGNO)"
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+ [(parallel
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+ [(set (reg:SI ARCV2_ACC)
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+ (plus:SI (mult:SI (zero_extend:SI (match_dup 1))
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+ (zero_extend:SI (match_dup 2)))
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+ (reg:SI ARCV2_ACC)))
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+ (clobber (reg:DI ARCV2_ACC))])
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+ (set (match_dup 0) (reg:SI ARCV2_ACC))]
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+ ""
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[(set_attr "length" "4")
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(set_attr "type" "multi")
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(set_attr "predicable" "no")
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126
packages/gcc/11.2.0/0008-arc-Fix-maddhisi-patterns.patch
vendored
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126
packages/gcc/11.2.0/0008-arc-Fix-maddhisi-patterns.patch
vendored
Normal file
@ -0,0 +1,126 @@
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From e73e3c3eaf2c3ea45083dda5dc4b7d29f6a03238 Mon Sep 17 00:00:00 2001
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From: Claudiu Zissulescu <claziss@synopsys.com>
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Date: Wed, 6 Oct 2021 09:47:50 +0300
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Subject: [PATCH] arc: Fix maddhisi patterns
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See for more details: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues/429
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---
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gcc/config/arc/arc.md | 43 +++++++---------------------------
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gcc/testsuite/gcc.target/arc/tmac-4.c | 29 ++++++++++++++++++++++
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2 files changed, 39 insertions(+), 33 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/arc/tmac-4.c
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--- a/gcc/config/arc/arc.md
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+++ b/gcc/config/arc/arc.md
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@@ -6055,33 +6055,22 @@
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(match_operand:SI 3 "register_operand" "")]
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"TARGET_PLUS_MACD"
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"{
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- rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
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+ rtx acc_reg = gen_rtx_REG (SImode, ACCL_REGNO);
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emit_move_insn (acc_reg, operands[3]);
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- emit_insn (gen_machi (operands[0], operands[1], operands[2]));
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+ emit_insn (gen_machi (operands[0], operands[1], operands[2], acc_reg));
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DONE;
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}")
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-(define_insn_and_split "machi"
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+(define_insn "machi"
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[(set (match_operand:SI 0 "register_operand" "=Ral,r")
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(plus:SI
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(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r,r"))
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(sign_extend:SI (match_operand:HI 2 "register_operand" "r,r")))
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- (reg:SI ARCV2_ACC)))
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+ (match_operand:SI 3 "accl_operand" "")))
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(clobber (reg:DI ARCV2_ACC))]
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"TARGET_PLUS_MACD"
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- "@
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- vmac2h\\t%0,%1,%2
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- #"
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- "&& reload_completed && (REGNO (operands[0]) != ACCL_REGNO)"
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- [(parallel
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- [(set (reg:SI ARCV2_ACC)
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- (plus:SI (mult:SI (sign_extend:SI (match_dup 1))
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- (sign_extend:SI (match_dup 2)))
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- (reg:SI ARCV2_ACC)))
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- (clobber (reg:DI ARCV2_ACC))])
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- (set (match_dup 0) (reg:SI ARCV2_ACC))]
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- ""
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+ "dmach\\t%0,%1,%2"
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[(set_attr "length" "4")
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(set_attr "type" "multi")
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(set_attr "predicable" "no")
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@@ -6095,34 +6084,22 @@
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(match_operand:SI 3 "register_operand" "")]
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"TARGET_PLUS_MACD"
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"{
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- rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
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+ rtx acc_reg = gen_rtx_REG (SImode, ACCL_REGNO);
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emit_move_insn (acc_reg, operands[3]);
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- emit_insn (gen_umachi (operands[0], operands[1], operands[2]));
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+ emit_insn (gen_umachi (operands[0], operands[1], operands[2], acc_reg));
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DONE;
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}")
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-
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-(define_insn_and_split "umachi"
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+(define_insn "umachi"
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[(set (match_operand:SI 0 "register_operand" "=Ral,r")
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(plus:SI
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(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r,r"))
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(zero_extend:SI (match_operand:HI 2 "register_operand" "r,r")))
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- (reg:SI ARCV2_ACC)))
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+ (match_operand:SI 3 "accl_operand" "")))
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(clobber (reg:DI ARCV2_ACC))]
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"TARGET_PLUS_MACD"
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- "@
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- vmac2hu\\t%0,%1,%2
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- #"
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- "&& reload_completed && (REGNO (operands[0]) != ACCL_REGNO)"
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||||||
|
- [(parallel
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||||||
|
- [(set (reg:SI ARCV2_ACC)
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||||||
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- (plus:SI (mult:SI (zero_extend:SI (match_dup 1))
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||||||
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- (zero_extend:SI (match_dup 2)))
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||||||
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- (reg:SI ARCV2_ACC)))
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- (clobber (reg:DI ARCV2_ACC))])
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- (set (match_dup 0) (reg:SI ARCV2_ACC))]
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- ""
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+ "dmachu\\t%0,%1,%2"
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[(set_attr "length" "4")
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(set_attr "type" "multi")
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(set_attr "predicable" "no")
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||||||
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--- /dev/null
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|
+++ b/gcc/testsuite/gcc.target/arc/tmac-4.c
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|
@@ -0,0 +1,29 @@
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|
+/* { dg-do compile } */
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|
+/* { dg-skip-if "" { ! { clmcpu } } } */
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|
+/* { dg-options "-O3 -mbig-endian -mcpu=hs38" } */
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|
+
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|
+struct a {};
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||||||
|
+struct b {
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|
+ int c;
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||||||
|
+ int d;
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||||||
|
+};
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|
+
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|
+struct {
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|
+ struct a e;
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|
+ struct b f[];
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|
+} g;
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|
+short h;
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|
+
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|
+extern void bar (int *);
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|
+
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|
+int foo(void)
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|
+{
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|
+ struct b *a;
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|
+ for (;;)
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|
+ {
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|
+ a = &g.f[h];
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+ bar(&a->d);
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|
+ }
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|
+}
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|
+
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||||||
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+/* { dg-final { scan-assembler "dmach" } } */
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||||||
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