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https://github.com/crosstool-ng/crosstool-ng.git
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168 lines
7.2 KiB
Diff
168 lines
7.2 KiB
Diff
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From eb49bbb886ef374eddb93e866c9c9f5f314c8014 Mon Sep 17 00:00:00 2001
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From: Richard Sandiford <richard.sandiford@arm.com>
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Date: Tue, 18 Jun 2024 12:22:31 +0100
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Subject: [PATCH 13/16] aarch64: Add some uses of force_lowpart_subreg
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This patch makes more use of force_lowpart_subreg, similarly
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to the recent patch for force_subreg. The criteria were:
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(1) The code is obviously specific to expand (where new pseudos
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can be created).
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(2) The value is obviously an rvalue rather than an lvalue.
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gcc/
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PR target/115464
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* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
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(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
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simplify_gen_subreg and lowpart_subreg.
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* config/aarch64/aarch64-sve-builtins-base.cc
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(svset_neonq_impl::expand): Likewise.
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* config/aarch64/aarch64-sve-builtins-sme.cc
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(add_load_store_slice_operand): Likewise.
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* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
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(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
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gcc/testsuite/
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PR target/115464
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* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
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(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
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---
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gcc/config/aarch64/aarch64-builtins.cc | 11 +++++------
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gcc/config/aarch64/aarch64-sve-builtins-base.cc | 2 +-
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gcc/config/aarch64/aarch64-sve-builtins-sme.cc | 2 +-
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gcc/config/aarch64/aarch64.cc | 14 +++++---------
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.../aarch64/sve/acle/general/pr115464_2.c | 11 +++++++++++
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5 files changed, 23 insertions(+), 17 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
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diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
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index b2e46a073a8..264b9560709 100644
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--- a/gcc/config/aarch64/aarch64-builtins.cc
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+++ b/gcc/config/aarch64/aarch64-builtins.cc
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@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
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int lane = INTVAL (lane_idx);
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if (lane < nunits / 4)
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- op2 = simplify_gen_subreg (d->mode, op2, quadmode,
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- subreg_lowpart_offset (d->mode, quadmode));
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+ op2 = force_lowpart_subreg (d->mode, op2, quadmode);
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else
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{
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/* Select the upper 64 bits, either a V2SF or V4HF, this however
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@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
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gen_highpart_mode generates code that isn't optimal. */
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rtx temp1 = gen_reg_rtx (d->mode);
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rtx temp2 = gen_reg_rtx (DImode);
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- temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
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- subreg_lowpart_offset (d->mode, quadmode));
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+ temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
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temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
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@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
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case AARCH64_WSR64:
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case AARCH64_WSRF64:
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case AARCH64_WSR128:
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- subreg = lowpart_subreg (sysreg_mode, input_val, mode);
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+ subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
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break;
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case AARCH64_WSRF:
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subreg = gen_lowpart_SUBREG (SImode, input_val);
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@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
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case AARCH64_RSR64:
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case AARCH64_RSRF64:
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case AARCH64_RSR128:
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- return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
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+ return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
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+ target, sysreg_mode);
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case AARCH64_RSRF:
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subreg = gen_lowpart_SUBREG (SImode, target);
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return gen_lowpart_SUBREG (SFmode, subreg);
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diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
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index 2c95da79572..3c970e9c5f8 100644
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--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
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+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
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@@ -1183,7 +1183,7 @@ public:
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if (BYTES_BIG_ENDIAN)
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return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
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insn_code icode = code_for_vcond_mask (mode, mode);
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- e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
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+ e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
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e.add_output_operand (icode);
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e.add_input_operand (icode, e.args[1]);
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e.add_input_operand (icode, e.args[0]);
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diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
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index f4c91bcbb95..b66b35ae60b 100644
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--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
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+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
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@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
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rtx base = e.args[argno];
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if (e.mode_suffix_id == MODE_vnum)
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{
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- rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
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+ rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
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base = simplify_gen_binary (PLUS, SImode, base, vnum);
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}
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e.add_input_operand (icode, base);
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diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
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index 1beec94629d..a064aeecbc0 100644
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--- a/gcc/config/aarch64/aarch64.cc
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+++ b/gcc/config/aarch64/aarch64.cc
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@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
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/* can_change_mode_class must only return true if subregs and svreinterprets
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have the same semantics. */
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if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
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- return lowpart_subreg (mode, x, GET_MODE (x));
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+ return force_lowpart_subreg (mode, x, GET_MODE (x));
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rtx res = gen_reg_rtx (mode);
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x = force_reg (GET_MODE (x), x);
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@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
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rtx *high_in2)
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{
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*low_dest = gen_reg_rtx (DImode);
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- *low_in1 = gen_lowpart (DImode, op1);
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- *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
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- subreg_lowpart_offset (DImode, TImode));
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+ *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
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+ *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
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*high_dest = gen_reg_rtx (DImode);
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*high_in1 = gen_highpart (DImode, op1);
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*high_in2 = simplify_gen_subreg (DImode, op2, TImode,
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@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
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rtx *high_in2)
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{
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*low_dest = gen_reg_rtx (DImode);
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- *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
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- subreg_lowpart_offset (DImode, TImode));
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-
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- *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
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- subreg_lowpart_offset (DImode, TImode));
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+ *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
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+ *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
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*high_dest = gen_reg_rtx (DImode);
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*high_in1 = simplify_gen_subreg (DImode, op1, TImode,
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diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
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new file mode 100644
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index 00000000000..f561c34f732
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
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@@ -0,0 +1,11 @@
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+/* { dg-options "-O2" } */
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+
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+#include <arm_neon.h>
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+#include <arm_sve.h>
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+#include <arm_neon_sve_bridge.h>
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+
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+svuint16_t
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+convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
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+{
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+ return svset_neonq_u16 (a, permute_tbl.val[1]);
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+}
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--
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2.44.2
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