mirror of
https://github.com/corda/corda.git
synced 2025-01-23 04:48:09 +00:00
merged ppc changes
This commit is contained in:
J. Treadwell
commit
ee90d7bd2c
416
src/powerpc.cpp
416
src/powerpc.cpp
@ -42,7 +42,7 @@ inline int SC(int op, int lev) { return op<<26|lev<<5|2; }
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inline int X(int op, int rt, int ra, int rb, int xo, int rc) { return op<<26|rt<<21|ra<<16|rb<<11|xo<<1|rc; }
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inline int XL(int op, int bt, int ba, int bb, int xo, int lk) { return op<<26|bt<<21|ba<<16|bb<<11|xo<<1|lk; }
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inline int XFX(int op, int rt, int spr, int xo) { return op<<26|rt<<21|spr<<11|xo<<1; }
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inline int XFL(int op, int flm, int frb, int xo, int rc) { return op<<26|flm<<17|frb<<11|xo<<1|rc; }
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inline int XFL(int op, int flm, int frb, int xo, int rc) { return op<<26|flm<<17|frb<<11|((xo&0x01f)<<6)|((xo>>5)<<1)|rc; }
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inline int XS(int op, int rs, int ra, int sh, int xo, int sh2, int rc) { return op<<26|rs<<21|ra<<16|sh<<11|xo<<2|sh2<<1|rc; }
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inline int XO(int op, int rt, int ra, int rb, int oe, int xo, int rc) { return op<<26|rt<<21|ra<<16|rb<<11|oe<<10|xo<<1|rc; }
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inline int A(int op, int frt, int fra, int frb, int frc, int xo, int rc) { return op<<26|frt<<21|fra<<16|frb<<11|frc<<6|xo<<1|rc; }
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@ -72,10 +72,10 @@ inline int addis(int rt, int ra, int i) { return D(15, rt, ra, i); }
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inline int subf(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 40, 0); }
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inline int subfc(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 8, 0); }
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inline int subfe(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 136, 0); }
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inline int _and(int rt, int ra, int rb) { return X(31, ra, rt, rb, 28, 0); }
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inline int and_(int rt, int ra, int rb) { return X(31, ra, rt, rb, 28, 0); }
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inline int andi(int rt, int ra, int i) { return D(28, ra, rt, i); }
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inline int andis(int rt, int ra, int i) { return D(29, ra, rt, i); }
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inline int _or(int rt, int ra, int rb) { return X(31, ra, rt, rb, 444, 0); }
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inline int or_(int rt, int ra, int rb) { return X(31, ra, rt, rb, 444, 0); }
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inline int ori(int rt, int ra, int i) { return D(24, rt, ra, i); }
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inline int oris(int rt, int ra, int i) { return D(25, rt, ra, i); }
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inline int rlwinm(int rt, int ra, int i, int mb, int me) { return M(21, ra, rt, i, mb, me, 0); }
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@ -89,6 +89,9 @@ inline int extsb(int rt, int rs) { return X(31, rs, rt, 0, 954, 0); }
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inline int extsh(int rt, int rs) { return X(31, rs, rt, 0, 922, 0); }
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inline int mfspr(int rt, int spr) { return XFX(31, rt, spr, 339); }
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inline int mtspr(int spr, int rs) { return XFX(31, rs, spr, 467); }
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inline int bl(int i) { return I(18, i, 0, 1); }
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inline int bcctr(int bo, int bi, int lk) { return XL(19, bo, bi, 0, 528, lk); }
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inline int bclr(int bo, int bi, int lk) { return XL(19, bo, bi, 0, 16, lk); }
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// PSEUDO-INSTRUCTIONS
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inline int li(int rt, int i) { return ori(rt, 0, i); }
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inline int lis(int rt, int i) { return oris(rt, 0, i); }
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@ -97,9 +100,13 @@ inline int srwi(int rt, int ra, int i) { return rlwinm(rt, ra, 32-i, i, 31); }
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inline int sub(int rt, int ra, int rb) { return subf(rt, rb, ra); }
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inline int subc(int rt, int ra, int rb) { return subfc(rt, rb, ra); }
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inline int subi(int rt, int ra, int i) { return addi(rt, ra, -i); }
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inline int mr(int rt, int ra) { return _or(rt, ra, ra); }
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inline int mr(int rt, int ra) { return or_(rt, ra, ra); }
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inline int mflr(int rx) { return mfspr(rx, 8); }
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inline int mtlr(int rx) { return mtspr(8, rx); }
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inline int mtctr(int rd) { return mtspr(9, rd); }
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inline int bctr() { return bcctr(20, 0, 0); }
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inline int bctrl() { return bcctr(20, 0, 1); }
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inline int blr() { return bclr(20, 0, 0); }
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}
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@ -166,8 +173,8 @@ typedef void (*BinaryOperationType)
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(Context*, unsigned, Assembler::Operand*, unsigned, Assembler::Operand*);
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typedef void (*TernaryOperationType)
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(Context*, unsigned, Assembler::Operand*, unsigned, Assembler::Operand*,
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unsigned, Assembler::Operand*);
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(Context*, unsigned, Assembler::Operand*, Assembler::Operand*,
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Assembler::Operand*);
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class ArchitectureContext {
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public:
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@ -243,6 +250,82 @@ offset(Context* c)
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Offset(c, c->lastBlock, c->code.length());
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}
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bool
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bounded(int right, int left, int32_t v)
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{
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return ((v << left) >> left) == v and ((v >> right) << right) == v;
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}
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void*
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updateOffset(System* s, uint8_t* instruction, bool conditional, int64_t value)
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{
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int32_t v = reinterpret_cast<uint8_t*>(value) - instruction - 4;
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if (conditional) {
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expect(s, bounded(2, 16, v));
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*reinterpret_cast<int32_t*>(instruction) |= v & 0xFFFC;
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} else {
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expect(s, bounded(2, 6, v));
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*reinterpret_cast<int32_t*>(instruction) |= v & 0x3FFFFFC;
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}
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*reinterpret_cast<int32_t*>(instruction) |= v;
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return instruction + 4;
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}
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class OffsetListener: public Promise::Listener {
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public:
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OffsetListener(System* s, uint8_t* instruction, bool conditional):
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s(s),
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instruction(instruction),
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conditional(conditional)
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{ }
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virtual void* resolve(int64_t value) {
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return updateOffset(s, instruction, conditional, value);
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}
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System* s;
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uint8_t* instruction;
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bool conditional;
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};
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class OffsetTask: public Task {
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public:
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OffsetTask(Task* next, Promise* promise, Promise* instructionOffset,
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bool conditional):
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Task(next),
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promise(promise),
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instructionOffset(instructionOffset),
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conditional(conditional)
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{ }
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virtual void run(Context* c) {
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if (promise->resolved()) {
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updateOffset
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(c->s, c->result + instructionOffset->value(), conditional,
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promise->value());
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} else {
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new (promise->listen(sizeof(OffsetListener)))
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OffsetListener(c->s, c->result + instructionOffset->value(),
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conditional);
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}
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}
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Promise* promise;
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Promise* instructionOffset;
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bool conditional;
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};
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void
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appendOffsetTask(Context* c, Promise* promise, Promise* instructionOffset,
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bool conditional)
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{
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c->tasks = new (c->zone->allocate(sizeof(OffsetTask))) OffsetTask
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(c->tasks, promise, instructionOffset, conditional);
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}
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inline unsigned
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index(UnaryOperation operation, OperandType operand)
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{
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@ -334,6 +417,88 @@ void unsignedShiftRightCRR(Context* con, unsigned size, Const* a, Reg* b, Reg* t
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issue(con, srwi(R(t), R(b), sh));
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}
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void
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updateImmediate(System* s, void* dst, int64_t src, unsigned size)
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{
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switch (size) {
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case 4: {
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static_cast<int32_t*>(dst)[0] |= src & 0xFFFF;
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static_cast<int32_t*>(dst)[1] |= src >> 16;
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} break;
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default: abort(s);
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}
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}
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class ImmediateListener: public Promise::Listener {
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public:
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ImmediateListener(System* s, void* dst, unsigned size, unsigned offset):
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s(s), dst(dst), size(size), offset(offset)
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{ }
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virtual void* resolve(int64_t value) {
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updateImmediate(s, dst, value, size);
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return static_cast<uint8_t*>(dst) + offset;
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}
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System* s;
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void* dst;
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unsigned size;
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unsigned offset;
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};
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class ImmediateTask: public Task {
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public:
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ImmediateTask(Task* next, Promise* promise, Promise* offset, unsigned size,
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unsigned promiseOffset):
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Task(next),
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promise(promise),
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offset(offset),
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size(size),
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promiseOffset(promiseOffset)
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{ }
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virtual void run(Context* c) {
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if (promise->resolved()) {
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updateImmediate
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(c->s, c->result + offset->value(), promise->value(), size);
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} else {
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new (promise->listen(sizeof(ImmediateListener))) ImmediateListener
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(c->s, c->result + offset->value(), size, promiseOffset);
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}
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}
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Promise* promise;
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Promise* offset;
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unsigned size;
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unsigned promiseOffset;
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};
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void
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appendImmediateTask(Context* c, Promise* promise, Promise* offset,
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unsigned size, unsigned promiseOffset = 0)
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{
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c->tasks = new (c->zone->allocate(sizeof(ImmediateTask))) ImmediateTask
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(c->tasks, promise, offset, size, promiseOffset);
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}
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void
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return_(Context* c)
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{
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issue(c, blr());
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}
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void
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jumpR(Context* c, unsigned size UNUSED, Assembler::Register* target)
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{
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assert(c, size == BytesPerWord);
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issue(c, mtctr(target->low));
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issue(c, bctr());
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}
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void
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moveRR(Context* c, unsigned srcSize, Assembler::Register* src,
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unsigned dstSize, Assembler::Register* dst);
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@ -349,7 +514,6 @@ swapRR(Context* c, unsigned aSize, Assembler::Register* a,
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moveRR(c, aSize, a, bSize, &tmp);
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moveRR(c, bSize, b, aSize, a);
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moveRR(c, bSize, &tmp, bSize, b);
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c->client->releaseTemporary(tmp.low);
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}
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void
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@ -394,17 +558,15 @@ moveRR(Context* c, unsigned srcSize, Assembler::Register* src,
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}
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}
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void moveCR(Context* con, unsigned aSize, Const* a, unsigned tSize, Reg* t) {
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int64_t i = getVal(a);
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if(tSize == 8) {
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int64_t j;
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if(aSize == 8) j = i; // 64-bit const -> load high bits into high register
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else j = 0; // 32-bit const -> clear high register
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issue(con, lis(H(t), hi16(hi32(j))));
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issue(con, ori(H(t), H(t), lo16(hi32(j))));
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void addCRR(Context* con, unsigned size, Const* a, Reg* b, Reg* t) {
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assert(con, size == BytesPerWord);
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int32_t i = getVal(a);
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if(i) {
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issue(con, addi(R(t), R(b), lo16(i)));
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if(hi16(i))
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issue(con, addis(R(t), R(t), hi16(i)));
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}
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issue(con, lis(R(t), hi16(i)));
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issue(con, ori(R(t), R(t), lo16(i)));
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}
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int
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@ -511,6 +673,53 @@ moveRM(Context* c, unsigned srcSize, Assembler::Register* src,
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store(c, srcSize, src, dst->base, dst->offset, dst->index, dst->scale, true);
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}
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void
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loadLinkRegisterR(Context* c, unsigned dstSize, Assembler::Register* dst)
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{
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assert(c, dstSize == BytesPerWord);
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issue(c, mflr(dst->low));
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}
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void
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storeLinkRegisterR(Context* c, unsigned srcSize, Assembler::Register* src)
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{
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assert(c, srcSize == BytesPerWord);
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issue(c, mtlr(src->low));
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}
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void addRRR(Context* con, unsigned size, Reg* a, Reg* b, Reg* t) {
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if(size == 8) {
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issue(con, addc(R(t), R(a), R(b)));
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issue(con, adde(H(t), H(a), H(b)));
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} else {
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issue(con, add(R(t), R(a), R(b)));
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}
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}
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void subRRR(Context* con, unsigned size, Reg* a, Reg* b, Reg* t) {
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if(size == 8) {
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issue(con, subfc(R(t), R(a), R(b)));
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issue(con, subfe(H(t), H(a), H(b)));
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} else {
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issue(con, subf(R(t), R(a), R(b)));
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}
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}
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void subCRR(Context* con, unsigned size, Const* a, Reg* b, Reg* t) {
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assert(con, size == BytesPerWord);
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int64_t i = getVal(a);
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if(i) {
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issue(con, subi(R(t), R(b), lo16(i)));
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issue(con, subi(R(t), R(t), hi16(i)));
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}
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}
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// END OPERATION COMPILERS
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void
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moveAndUpdateRM(Context* c, unsigned srcSize, Assembler::Register* src,
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unsigned dstSize UNUSED, Assembler::Memory* dst)
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@ -598,76 +807,149 @@ moveMR(Context* c, unsigned srcSize, Assembler::Memory* src,
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}
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void
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loadLinkRegisterR(Context* c, unsigned dstSize, Assembler::Register* dst)
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moveCR2(Context* c, unsigned, Assembler::Constant* src,
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unsigned dstSize, Assembler::Register* dst, unsigned promiseOffset)
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{
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assert(c, dstSize == BytesPerWord);
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issue(c, mflr(dst->low));
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if (dstSize == 4) {
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if (src->value->resolved()) {
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int32_t v = src->value->value();
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issue(c, li(dst->low, v));
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if (v >> 16) {
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issue(c, lis(dst->low, v >> 16));
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}
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} else {
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appendImmediateTask
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(c, src->value, offset(c), BytesPerWord, promiseOffset);
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issue(c, li(dst->low, 0));
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issue(c, lis(dst->low, 0));
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}
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} else {
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abort(c); // todo
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}
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}
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|
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void
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storeLinkRegisterR(Context* c, unsigned srcSize, Assembler::Register* src)
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moveCR(Context* c, unsigned srcSize, Assembler::Constant* src,
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unsigned dstSize, Assembler::Register* dst)
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{
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assert(c, srcSize == BytesPerWord);
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issue(c, mtlr(src->low));
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moveCR2(c, srcSize, src, dstSize, dst, 0);
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}
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void addRRR(Context* con, unsigned size, Reg* a, Reg* b, Reg* t) {
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if(size == 8) {
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issue(con, addc(R(t), R(a), R(b)));
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issue(con, adde(H(t), H(a), H(b)));
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} else {
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issue(con, add(R(t), R(a), R(b)));
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}
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}
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void addCRR(Context* con, unsigned size, Const* a, Reg* b, Reg* t) {
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assert(con, size == BytesPerWord);
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void moveCR3(Context* con, unsigned aSize, Const* a, unsigned tSize, Reg* t) {
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int64_t i = getVal(a);
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if(i) {
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issue(con, addi(R(t), R(b), lo16(i)));
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issue(con, addi(R(t), R(t), hi16(i)));
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if(tSize == 8) {
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int64_t j;
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if(aSize == 8) j = i; // 64-bit const -> load high bits into high register
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else j = 0; // 32-bit const -> clear high register
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issue(con, lis(H(t), hi16(hi32(j))));
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issue(con, ori(H(t), H(t), lo16(hi32(j))));
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}
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issue(con, lis(R(t), hi16(i)));
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issue(con, ori(R(t), R(t), lo16(i)));
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}
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ShiftMaskPromise*
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shiftMaskPromise(Context* c, Promise* base, unsigned shift, int64_t mask)
|
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{
|
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return new (c->zone->allocate(sizeof(ShiftMaskPromise)))
|
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ShiftMaskPromise(base, shift, mask);
|
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}
|
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|
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void
|
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moveCM(Context* c, unsigned srcSize, Assembler::Constant* src,
|
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unsigned dstSize, Assembler::Memory* dst)
|
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{
|
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switch (dstSize) {
|
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case 8: {
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Assembler::Constant srcHigh
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(shiftMaskPromise(c, src->value, 32, 0xFFFFFFFF));
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Assembler::Constant srcLow
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(shiftMaskPromise(c, src->value, 0, 0xFFFFFFFF));
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|
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Assembler::Memory dstLow
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(dst->base, dst->offset + 4, dst->index, dst->scale);
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moveCM(c, 4, &srcLow, 4, &dstLow);
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moveCM(c, 4, &srcHigh, 4, dst);
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} break;
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default:
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Assembler::Register tmp(c->client->acquireTemporary());
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moveCR(c, srcSize, src, dstSize, &tmp);
|
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moveRM(c, dstSize, &tmp, dstSize, dst);
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}
|
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}
|
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|
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void subRRR(Context* con, unsigned size, Reg* a, Reg* b, Reg* t) {
|
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if(size == 8) {
|
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issue(con, subfc(R(t), R(a), R(b)));
|
||||
issue(con, subfe(H(t), H(a), H(b)));
|
||||
} else {
|
||||
issue(con, subf(R(t), R(a), R(b)));
|
||||
}
|
||||
void
|
||||
callR(Context* c, unsigned size, Assembler::Register* target)
|
||||
{
|
||||
assert(c, size == BytesPerWord);
|
||||
|
||||
issue(c, mtctr(target->low));
|
||||
issue(c, bctrl());
|
||||
}
|
||||
|
||||
void subCRR(Context* con, unsigned size, Const* a, Reg* b, Reg* t) {
|
||||
assert(con, size == BytesPerWord);
|
||||
void
|
||||
callC(Context* c, unsigned size, Assembler::Constant* target)
|
||||
{
|
||||
assert(c, size == BytesPerWord);
|
||||
|
||||
int64_t i = getVal(a);
|
||||
if(i) {
|
||||
issue(con, subi(R(t), R(b), lo16(i)));
|
||||
issue(con, subi(R(t), R(t), hi16(i)));
|
||||
}
|
||||
appendOffsetTask(c, target->value, offset(c), false);
|
||||
issue(c, bl(0));
|
||||
}
|
||||
|
||||
void
|
||||
longCallC(Context* c, unsigned size, Assembler::Constant* target)
|
||||
{
|
||||
assert(c, size == BytesPerWord);
|
||||
|
||||
Assembler::Register tmp(0);
|
||||
moveCR2(c, BytesPerWord, target, BytesPerWord, &tmp, 12);
|
||||
callR(c, BytesPerWord, &tmp);
|
||||
}
|
||||
|
||||
void
|
||||
longJumpC(Context* c, unsigned size, Assembler::Constant* target)
|
||||
{
|
||||
assert(c, size == BytesPerWord);
|
||||
|
||||
Assembler::Register tmp(0);
|
||||
moveCR2(c, BytesPerWord, target, BytesPerWord, &tmp, 12);
|
||||
jumpR(c, BytesPerWord, &tmp);
|
||||
}
|
||||
|
||||
// END OPERATION COMPILERS
|
||||
|
||||
|
||||
void
|
||||
populateTables(ArchitectureContext* /*c*/)
|
||||
populateTables(ArchitectureContext* c)
|
||||
{
|
||||
// const OperandType C = ConstantOperand;
|
||||
const OperandType C = ConstantOperand;
|
||||
// const OperandType A = AddressOperand;
|
||||
// const OperandType R = RegisterOperand;
|
||||
// const OperandType M = MemoryOperand;
|
||||
const OperandType R = RegisterOperand;
|
||||
const OperandType M = MemoryOperand;
|
||||
|
||||
// OperationType* zo = c->operations;
|
||||
// UnaryOperationType* uo = c->unaryOperations;
|
||||
// BinaryOperationType* bo = c->binaryOperations;
|
||||
OperationType* zo = c->operations;
|
||||
UnaryOperationType* uo = c->unaryOperations;
|
||||
BinaryOperationType* bo = c->binaryOperations;
|
||||
// TernaryOperationType* to = c->ternaryOperations;
|
||||
|
||||
|
||||
zo[Return] = return_;
|
||||
|
||||
uo[index(LongCall, C)] = CAST1(longCallC);
|
||||
|
||||
uo[index(LongJump, C)] = CAST1(longJumpC);
|
||||
|
||||
uo[index(Jump, R)] = CAST1(jumpR);
|
||||
|
||||
uo[index(Call, C)] = CAST1(callC);
|
||||
uo[index(AlignedCall, C)] = CAST1(callC);
|
||||
|
||||
bo[index(Move, R, R)] = CAST2(moveRR);
|
||||
bo[index(Move, C, R)] = CAST2(moveCR);
|
||||
bo[index(Move, C, M)] = CAST2(moveCM);
|
||||
bo[index(Move, M, R)] = CAST2(moveMR);
|
||||
bo[index(Move, R, M)] = CAST2(moveRM);
|
||||
}
|
||||
|
||||
class MyArchitecture: public Assembler::Architecture {
|
||||
@ -814,7 +1096,7 @@ class MyArchitecture: public Assembler::Architecture {
|
||||
case Add:
|
||||
case Subtract:
|
||||
if (BytesPerWord == 4 and aSize == 8) {
|
||||
aTypeMask = bTypeMask = (1 << RegisterOperand);
|
||||
*aTypeMask = *bTypeMask = (1 << RegisterOperand);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -918,7 +1200,7 @@ class MyAssembler: public Assembler {
|
||||
|
||||
virtual void allocateFrame(unsigned footprint) {
|
||||
Register returnAddress(0);
|
||||
loadLinkRegisterR(&c, BytesPerWord, &returnAddress);
|
||||
issue(&c, mflr(returnAddress.low));
|
||||
|
||||
Memory returnAddressDst(StackRegister, 8);
|
||||
moveRM(&c, BytesPerWord, &returnAddress, BytesPerWord, &returnAddressDst);
|
||||
@ -937,7 +1219,7 @@ class MyAssembler: public Assembler {
|
||||
Memory returnAddressSrc(StackRegister, 8);
|
||||
moveMR(&c, BytesPerWord, &returnAddressSrc, BytesPerWord, &returnAddress);
|
||||
|
||||
storeLinkRegisterR(&c, BytesPerWord, &returnAddress);
|
||||
issue(&c, mtlr(returnAddress.low));
|
||||
}
|
||||
|
||||
virtual void apply(Operation op) {
|
||||
@ -959,7 +1241,7 @@ class MyAssembler: public Assembler {
|
||||
}
|
||||
|
||||
virtual void apply(TernaryOperation op,
|
||||
unsigned aSize, OperandType aType, Operand* aOperand,
|
||||
unsigned, OperandType aType, Operand* aOperand,
|
||||
unsigned bSize, OperandType bType UNUSED,
|
||||
Operand* bOperand,
|
||||
unsigned cSize, OperandType cType UNUSED,
|
||||
@ -970,7 +1252,7 @@ class MyAssembler: public Assembler {
|
||||
assert(&c, cType == RegisterOperand);
|
||||
|
||||
arch_->c.ternaryOperations[index(op, aType)]
|
||||
(&c, aSize, aOperand, bSize, bOperand, cSize, cOperand);
|
||||
(&c, bSize, aOperand, bOperand, cOperand);
|
||||
}
|
||||
|
||||
virtual void writeTo(uint8_t* dst) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user