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handle logical AND with a constant in a single instruction where possible
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parent
bd01784249
commit
dd0a696932
51
src/arm.cpp
51
src/arm.cpp
@ -82,6 +82,7 @@ inline int subi(int Rd, int Rn, int imm, int rot=0) { return DATAI(AL, 0x2, 0, R
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inline int rsbi(int Rd, int Rn, int imm, int rot=0) { return DATAI(AL, 0x3, 0, Rn, Rd, rot, imm); }
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inline int rsbi(int Rd, int Rn, int imm, int rot=0) { return DATAI(AL, 0x3, 0, Rn, Rd, rot, imm); }
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inline int addi(int Rd, int Rn, int imm, int rot=0) { return DATAI(AL, 0x4, 0, Rn, Rd, rot, imm); }
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inline int addi(int Rd, int Rn, int imm, int rot=0) { return DATAI(AL, 0x4, 0, Rn, Rd, rot, imm); }
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inline int adci(int Rd, int Rn, int imm, int rot=0) { return DATAI(AL, 0x5, 0, Rn, Rd, rot, imm); }
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inline int adci(int Rd, int Rn, int imm, int rot=0) { return DATAI(AL, 0x5, 0, Rn, Rd, rot, imm); }
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inline int bici(int Rd, int Rn, int imm, int rot=0) { return DATAI(AL, 0xe, 0, Rn, Rd, rot, imm); }
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inline int cmpi(int Rn, int imm, int rot=0) { return DATAI(AL, 0xa, 1, Rn, 0, rot, imm); }
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inline int cmpi(int Rn, int imm, int rot=0) { return DATAI(AL, 0xa, 1, Rn, 0, rot, imm); }
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inline int orri(int Rd, int Rn, int imm, int rot=0) { return DATAI(AL, 0xc, 0, Rn, Rd, rot, imm); }
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inline int orri(int Rd, int Rn, int imm, int rot=0) { return DATAI(AL, 0xc, 0, Rn, Rd, rot, imm); }
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inline int movi(int Rd, int imm, int rot=0) { return DATAI(AL, 0xd, 0, 0, Rd, rot, imm); }
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inline int movi(int Rd, int imm, int rot=0) { return DATAI(AL, 0xd, 0, 0, Rd, rot, imm); }
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@ -1023,6 +1024,54 @@ andR(Context* c, unsigned size, Assembler::Register* a,
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emit(c, and_(dst->low, a->low, b->low));
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emit(c, and_(dst->low, a->low, b->low));
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}
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}
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void
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andC(Context* c, unsigned size, Assembler::Constant* a,
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Assembler::Register* b, Assembler::Register* dst)
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{
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int64_t v = a->value->value();
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if (size == 8) {
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ResolvedPromise high((v >> 32) & 0xFFFFFFFF);
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Assembler::Constant ah(&high);
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ResolvedPromise low(v & 0xFFFFFFFF);
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Assembler::Constant al(&low);
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Assembler::Register bh(b->high);
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Assembler::Register dh(dst->high);
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andC(c, 4, &al, b, dst);
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andC(c, 4, &ah, &bh, &dh);
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} else {
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uint32_t v32 = static_cast<uint32_t>(v);
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if (v32 != 0xFFFFFFFF) {
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if ((v32 & 0xFFFFFF00) == 0xFFFFFF00) {
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emit(c, bici(dst->low, b->low, (~(v32 & 0xFF)) & 0xFF));
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} else if ((v32 & 0xFFFFFF00) == 0) {
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emit(c, andi(dst->low, b->low, v32 & 0xFF));
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} else {
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// todo: there are other cases we can handle in one
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// instruction
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bool useTemporary = b->low == dst->low;
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Assembler::Register tmp(dst->low);
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if (useTemporary) {
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tmp.low = c->client->acquireTemporary();
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}
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moveCR(c, 4, a, 4, &tmp);
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andR(c, 4, b, &tmp, dst);
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if (useTemporary) {
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c->client->releaseTemporary(tmp.low);
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}
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}
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} else {
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moveRR(c, size, b, size, dst);
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}
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}
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}
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void
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void
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orR(Context* c, unsigned size, Assembler::Register* a,
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orR(Context* c, unsigned size, Assembler::Register* a,
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Assembler::Register* b, Assembler::Register* dst)
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Assembler::Register* b, Assembler::Register* dst)
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@ -1486,6 +1535,7 @@ populateTables(ArchitectureContext* c)
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to[index(c, UnsignedShiftRight, C)] = CAST3(unsignedShiftRightC);
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to[index(c, UnsignedShiftRight, C)] = CAST3(unsignedShiftRightC);
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to[index(c, And, R)] = CAST3(andR);
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to[index(c, And, R)] = CAST3(andR);
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to[index(c, And, C)] = CAST3(andC);
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to[index(c, Or, R)] = CAST3(orR);
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to[index(c, Or, R)] = CAST3(orR);
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@ -1779,7 +1829,6 @@ class MyArchitecture: public Assembler::Architecture {
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case Add:
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case Add:
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case Subtract:
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case Subtract:
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case And:
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case Or:
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case Or:
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case Xor:
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case Xor:
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case Multiply:
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case Multiply:
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