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Debugging VFP support on ARM.
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JET
parent
47b91f38ee
commit
9b1b07bd88
73
src/arm.cpp
73
src/arm.cpp
@ -230,9 +230,11 @@ inline int ble(int offset) { return SETCOND(b(offset), LE); }
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inline int bge(int offset) { return SETCOND(b(offset), GE); }
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inline int blo(int offset) { return SETCOND(b(offset), CC); }
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inline int bhs(int offset) { return SETCOND(b(offset), CS); }
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inline int bpl(int offset) { return SETCOND(b(offset), PL); }
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inline int fmstat() { return fmrx(15, FPSCR); }
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// HARDWARE FLAGS
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bool vfpSupported() {
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return false; // TODO
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return true; // TODO
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}
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}
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@ -1107,8 +1109,10 @@ void floatAbsoluteRR(Context* con, unsigned size, Assembler::Register* a, unsign
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void floatNegateRR(Context* con, unsigned size, Assembler::Register* a, unsigned UNUSED, Assembler::Register* b) {
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if (size == 8) {
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/**/fprintf(stderr, ">>>>>>>>>>>>>>>>>>>>>>>> invalid 64-bit Scheiße\n");
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emit(con, fnegd(b->low, a->low));
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} else {
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/**/fprintf(stderr, ">>>>>>>>>>>>>>>>>>>>>>>> %d <- -%d\n", b->low, a->low);
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emit(con, fnegs(b->low, a->low));
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}
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}
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@ -1282,7 +1286,7 @@ store(Context* con, unsigned size, Assembler::Register* src,
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or (size != 2 and abs(offset) == (abs(offset) & 0xFFF)))
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{
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if (isFpr(src)) {
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/**/fprintf(stderr, ">>>>>>>>>>>>>>>>>>>>>>>> fpr store offset -> %d\n", src->low);
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/**/fprintf(stderr, ">>>>>>>>>>>>>>>>>>>>>>>> [%d + 0x%x] <- %d\n", base, offset, src->low);
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if (size == 4) emit(con, fsts(toFpr(src), base, offset));
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else abort(con);
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} else {
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@ -1415,7 +1419,7 @@ load(Context* con, unsigned srcSize, int base, int offset, int index,
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and abs(offset) == (abs(offset) & 0xFFF)))
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{
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if (isFpr(dst)) {
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/**/fprintf(stderr, ">>>>>>>>>>>>>>>>>>>>>>>> fpr load offset <- %d\n", dst->low);
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/**/fprintf(stderr, ">>>>>>>>>>>>>>>>>>>>>>>> %d <- [%d + 0x%x]\n", dst->low, base, offset);
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if (srcSize == 4) emit(con, flds(toFpr(dst), base, offset));
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else abort(con);
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} else {
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@ -1583,8 +1587,13 @@ compareRR(Context* c, unsigned aSize UNUSED, Assembler::Register* a,
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{
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assert(c, aSize == 4 and bSize == 4);
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assert(c, b->low != a->low);
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assert(c, !(isFpr(a) ^ isFpr(b)));
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emit(c, cmp(b->low, a->low));
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if (isFpr(a)) {
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emit(c, fcmps(toFpr(b), toFpr(a)));
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emit(c, fmstat());
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}
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else emit(c, cmp(b->low, a->low));
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}
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void
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@ -1593,7 +1602,8 @@ compareCR(Context* c, unsigned aSize, Assembler::Constant* a,
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{
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assert(c, aSize == 4 and bSize == 4);
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if (a->value->resolved() and isOfWidth(a->value->value(), 8)) {
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if (!isFpr(b) && a->value->resolved() &&
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isOfWidth(a->value->value(), 8)) {
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emit(c, cmpi(b->low, a->value->value()));
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} else {
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Assembler::Register tmp(c->client->acquireTemporary());
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@ -1632,23 +1642,37 @@ branch(Context* c, TernaryOperation op)
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{
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switch (op) {
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case JumpIfEqual:
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case JumpIfFloatEqual:
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return beq(0);
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case JumpIfNotEqual:
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case JumpIfFloatNotEqual:
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return bne(0);
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case JumpIfLess:
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case JumpIfFloatLess:
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case JumpIfFloatLessOrUnordered:
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return blt(0);
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case JumpIfGreater:
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case JumpIfFloatGreater:
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return bgt(0);
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case JumpIfLessOrEqual:
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case JumpIfFloatLessOrEqual:
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case JumpIfFloatLessOrEqualOrUnordered:
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return ble(0);
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case JumpIfGreaterOrEqual:
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case JumpIfFloatGreaterOrEqual:
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return bge(0);
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case JumpIfFloatGreaterOrUnordered:
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return bhi(0);
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case JumpIfFloatGreaterOrEqualOrUnordered:
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return bpl(0);
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default:
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abort(c);
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}
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@ -1763,10 +1787,12 @@ branchRR(Context* c, TernaryOperation op, unsigned size,
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}
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void
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branchCR(Context* c, TernaryOperation op, unsigned size,
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branchCR(Context* con, TernaryOperation op, unsigned size,
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Assembler::Constant* a, Assembler::Register* b,
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Assembler::Constant* target)
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{
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assert(con, !isFloatBranch(op));
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if (size > TargetBytesPerWord) {
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int64_t v = a->value->value();
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@ -1778,34 +1804,36 @@ branchCR(Context* c, TernaryOperation op, unsigned size,
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Assembler::Register bh(b->high);
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branchLong(c, op, &al, &ah, b, &bh, target, CAST2(compareCR),
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branchLong(con, op, &al, &ah, b, &bh, target, CAST2(compareCR),
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CAST2(compareCR));
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} else {
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compareCR(c, size, a, size, b);
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branch(c, op, target);
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compareCR(con, size, a, size, b);
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branch(con, op, target);
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}
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}
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void
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branchRM(Context* c, TernaryOperation op, unsigned size,
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branchRM(Context* con, TernaryOperation op, unsigned size,
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Assembler::Register* a, Assembler::Memory* b,
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Assembler::Constant* target)
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{
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assert(c, size <= TargetBytesPerWord);
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assert(con, !isFloatBranch(op));
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assert(con, size <= TargetBytesPerWord);
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compareRM(c, size, a, size, b);
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branch(c, op, target);
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compareRM(con, size, a, size, b);
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branch(con, op, target);
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}
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void
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branchCM(Context* c, TernaryOperation op, unsigned size,
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branchCM(Context* con, TernaryOperation op, unsigned size,
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Assembler::Constant* a, Assembler::Memory* b,
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Assembler::Constant* target)
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{
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assert(c, size <= TargetBytesPerWord);
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assert(con, !isFloatBranch(op));
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assert(con, size <= TargetBytesPerWord);
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compareCM(c, size, a, size, b);
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branch(c, op, target);
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compareCM(con, size, a, size, b);
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branch(con, op, target);
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}
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ShiftMaskPromise*
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@ -2304,7 +2332,6 @@ class MyArchitecture: public Assembler::Architecture {
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if (vfpSupported()) {
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*aTypeMask = (1 << RegisterOperand);
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*aRegisterMask = FPR_MASK;
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*thunk = true;
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} else {
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*thunk = true;
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}
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@ -2314,7 +2341,6 @@ class MyArchitecture: public Assembler::Architecture {
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if (vfpSupported() && bSize == 4 && aSize == 4) {
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*aTypeMask = (1 << RegisterOperand);
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*aRegisterMask = FPR_MASK;
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*thunk = true;
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} else {
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*thunk = true;
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}
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@ -2324,7 +2350,6 @@ class MyArchitecture: public Assembler::Architecture {
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if (vfpSupported() && aSize == 4 && bSize == 4) {
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*aTypeMask = (1 << RegisterOperand);
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*aRegisterMask = FPR_MASK;
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*thunk = true;
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} else {
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*thunk = true;
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}
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@ -2421,8 +2446,12 @@ class MyArchitecture: public Assembler::Architecture {
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case JumpIfFloatGreaterOrUnordered:
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case JumpIfFloatLessOrEqualOrUnordered:
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case JumpIfFloatGreaterOrEqualOrUnordered:
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if (vfpSupported()) *thunk = true;
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else *thunk = true;
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if (vfpSupported()) {
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*aTypeMask = *bTypeMask = (1 << RegisterOperand);
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*aRegisterMask = *bRegisterMask = FPR_MASK;
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} else {
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*thunk = true;
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}
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break;
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default:
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