From 89a2739165d4ea5bc279fa7290bf85c9a7d3a8b6 Mon Sep 17 00:00:00 2001
From: Joel Dice <git@seibutsu.mailsnare.net>
Date: Mon, 9 Mar 2009 08:26:23 -0600
Subject: [PATCH] sync instruction cache after compiling a method

---
 src/compile.cpp |  2 ++
 src/powerpc.h   | 23 +++++++++++++++++++++++
 src/x86.h       |  5 +++++
 3 files changed, 30 insertions(+)

diff --git a/src/compile.cpp b/src/compile.cpp
index 93d7422638..bd1b3367b5 100644
--- a/src/compile.cpp
+++ b/src/compile.cpp
@@ -4259,6 +4259,8 @@ finish(MyThread* t, Allocator* allocator, Context* context)
     trap();
   }
 
+  syncInstructionCache(start, codeSize);
+
   return start;
 }
 
diff --git a/src/powerpc.h b/src/powerpc.h
index fbc8753b44..0d983f8118 100644
--- a/src/powerpc.h
+++ b/src/powerpc.h
@@ -67,6 +67,29 @@ loadMemoryBarrier()
   memoryBarrier();
 }
 
+inline void
+syncInstructionCache(const void* start, unsigned size)
+{
+  const unsigned CacheLineSize = 32;
+  const uintptr_t Mask = ~(CacheLineSize - 1);
+
+  uintptr_t cacheLineStart = reinterpret_cast<uintptr_t>(start) & Mask;
+  uintptr_t cacheLineEnd
+    = (reinterpret_cast<uintptr_t>(start) + size + CacheLineSize - 1) & Mask;
+
+  for (uintptr_t p = cacheLineStart; p < cacheLineEnd; p += CacheLineSize) {
+    __asm__ __volatile__("dcbf 0, %0" : : "r" (p));
+  }
+
+  __asm__ __volatile__("sync");
+
+  for (uintptr_t p = cacheLineStart; p < cacheLineEnd; p += CacheLineSize) {
+    __asm__ __volatile__("icbi 0, %0" : : "r" (p));
+  }
+
+  __asm__ __volatile__("isync");
+}
+
 inline uint64_t
 dynamicCall(void* function, uintptr_t* arguments, uint8_t* argumentTypes,
             unsigned argumentCount, unsigned argumentsSize,
diff --git a/src/x86.h b/src/x86.h
index 578d27690b..b66916b7b7 100644
--- a/src/x86.h
+++ b/src/x86.h
@@ -71,6 +71,11 @@ loadMemoryBarrier()
   memoryBarrier();
 }
 
+inline void
+syncInstructionCache(const void*, unsigned)
+{
+  // ignore
+}
 
 inline uint64_t
 dynamicCall(void* function, uintptr_t* arguments, uint8_t*,