From 7c24701d3796b5e04c267cc6899bba65c5e0ca7b Mon Sep 17 00:00:00 2001 From: "joshuawarner32@gmail.com" Date: Thu, 4 Dec 2014 22:06:55 -0700 Subject: [PATCH] transition x86 registers to Register instances --- include/avian/codegen/registers.h | 2 +- src/codegen/target/x86/assembler.cpp | 18 +++---- src/codegen/target/x86/operations.cpp | 2 +- src/codegen/target/x86/registers.h | 75 +++++++++++++-------------- 4 files changed, 46 insertions(+), 51 deletions(-) diff --git a/include/avian/codegen/registers.h b/include/avian/codegen/registers.h index d86b122715..89b22f6668 100644 --- a/include/avian/codegen/registers.h +++ b/include/avian/codegen/registers.h @@ -31,7 +31,7 @@ public: return !(*this == o); } - constexpr explicit operator int8_t() const { + constexpr operator int8_t() const { return index; } }; diff --git a/src/codegen/target/x86/assembler.cpp b/src/codegen/target/x86/assembler.cpp index 21a89e8362..ca928137f3 100644 --- a/src/codegen/target/x86/assembler.cpp +++ b/src/codegen/target/x86/assembler.cpp @@ -236,11 +236,11 @@ class MyArchitecture : public Architecture { virtual bool reserved(Register register_) { switch ((int8_t)register_) { - case rbp: + case (int8_t)rbp: return UseFramePointer; - case rsp: - case rbx: + case (int8_t)rsp: + case (int8_t)rbx: return true; default: @@ -602,13 +602,13 @@ class MyArchitecture : public Architecture { if (aSize == 4 and bSize == 8) { aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair) | (1 << (unsigned)lir::Operand::Type::Memory); - const uint32_t mask = GeneralRegisterMask + const RegisterMask mask = GeneralRegisterMask & ~((1 << rax) | (1 << rdx)); aMask.setLowHighRegisterMasks(mask, mask); } else if (aSize == 1 or bSize == 1) { aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair) | (1 << (unsigned)lir::Operand::Type::Memory); - const uint32_t mask = (1 << rax) | (1 << rcx) | (1 << rdx) + const RegisterMask mask = (1 << rax) | (1 << rcx) | (1 << rdx) | (1 << rbx); aMask.setLowHighRegisterMasks(mask, mask); } @@ -681,7 +681,7 @@ class MyArchitecture : public Architecture { if (aSize == 4 and bSize == 8) { bMask.setLowHighRegisterMasks(1 << rax, 1 << rdx); } else if (aSize == 1 or bSize == 1) { - const uint32_t mask = (1 << rax) | (1 << rcx) | (1 << rdx) + const RegisterMask mask = (1 << rax) | (1 << rcx) | (1 << rdx) | (1 << rbx); bMask.setLowHighRegisterMasks(mask, mask); } @@ -775,7 +775,7 @@ class MyArchitecture : public Architecture { case lir::Multiply: if (TargetBytesPerWord == 4 and aSize == 8) { - const uint32_t mask = GeneralRegisterMask & ~((1 << rax) | (1 << rdx)); + const RegisterMask mask = GeneralRegisterMask & ~((1 << rax) | (1 << rdx)); aMask.setLowHighRegisterMasks(mask, mask); bMask.setLowHighRegisterMasks(mask, 1 << rdx); } else { @@ -808,12 +808,12 @@ class MyArchitecture : public Architecture { case lir::ShiftRight: case lir::UnsignedShiftRight: { if (TargetBytesPerWord == 4 and bSize == 8) { - const uint32_t mask = GeneralRegisterMask & ~(1 << rcx); + const RegisterMask mask = GeneralRegisterMask & ~(1 << rcx); aMask.setLowHighRegisterMasks(mask, mask); bMask.setLowHighRegisterMasks(mask, mask); } else { aMask.setLowHighRegisterMasks(static_cast(1) << rcx, GeneralRegisterMask); - const uint32_t mask = GeneralRegisterMask & ~(1 << rcx); + const RegisterMask mask = GeneralRegisterMask & ~(1 << rcx); bMask.setLowHighRegisterMasks(mask, mask); } } break; diff --git a/src/codegen/target/x86/operations.cpp b/src/codegen/target/x86/operations.cpp index c61ef64477..a37b6f3f61 100644 --- a/src/codegen/target/x86/operations.cpp +++ b/src/codegen/target/x86/operations.cpp @@ -991,7 +991,7 @@ void multiplyRR(Context* c, addRR(c, 4, scratch, 4, &bh); moveRR(c, 4, &axdx, 4, b); - if (tmp.low != -1) { + if (tmp.low != NoRegister) { c->client->releaseTemporary(tmp.low); } } else { diff --git a/src/codegen/target/x86/registers.h b/src/codegen/target/x86/registers.h index b61e521b7c..79b1218b13 100644 --- a/src/codegen/target/x86/registers.h +++ b/src/codegen/target/x86/registers.h @@ -15,50 +15,45 @@ namespace avian { namespace codegen { namespace x86 { -enum { - rax = 0, - rcx = 1, - rdx = 2, - rbx = 3, - rsp = 4, - rbp = 5, - rsi = 6, - rdi = 7, - r8 = 8, - r9 = 9, - r10 = 10, - r11 = 11, - r12 = 12, - r13 = 13, - r14 = 14, - r15 = 15, -}; +constexpr Register rax((int)0); +constexpr Register rcx(1); +constexpr Register rdx(2); +constexpr Register rbx(3); +constexpr Register rsp(4); +constexpr Register rbp(5); +constexpr Register rsi(6); +constexpr Register rdi(7); +constexpr Register r8(8); +constexpr Register r9(9); +constexpr Register r10(10); +constexpr Register r11(11); +constexpr Register r12(12); +constexpr Register r13(13); +constexpr Register r14(14); +constexpr Register r15(15); +constexpr Register xmm0(16); +constexpr Register xmm1(16 + 1); +constexpr Register xmm2(16 + 2); +constexpr Register xmm3(16 + 3); +constexpr Register xmm4(16 + 4); +constexpr Register xmm5(16 + 5); +constexpr Register xmm6(16 + 6); +constexpr Register xmm7(16 + 7); +constexpr Register xmm8(16 + 8); +constexpr Register xmm9(16 + 9); +constexpr Register xmm10(16 + 10); +constexpr Register xmm11(16 + 11); +constexpr Register xmm12(16 + 12); +constexpr Register xmm13(16 + 13); +constexpr Register xmm14(16 + 14); +constexpr Register xmm15(16 + 15); -enum { - xmm0 = r15 + 1, - xmm1, - xmm2, - xmm3, - xmm4, - xmm5, - xmm6, - xmm7, - xmm8, - xmm9, - xmm10, - xmm11, - xmm12, - xmm13, - xmm14, - xmm15, -}; +constexpr Register LongJumpRegister = r10; -const int LongJumpRegister = r10; - -const unsigned GeneralRegisterMask = vm::TargetBytesPerWord == 4 ? 0x000000ff +constexpr RegisterMask GeneralRegisterMask = vm::TargetBytesPerWord == 4 ? 0x000000ff : 0x0000ffff; -const unsigned FloatRegisterMask = vm::TargetBytesPerWord == 4 ? 0x00ff0000 +constexpr RegisterMask FloatRegisterMask = vm::TargetBytesPerWord == 4 ? 0x00ff0000 : 0xffff0000; } // namespace x86