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get rid of implicit Register casts

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joshuawarner32@gmail.com 2014-12-04 22:15:40 -07:00 committed by Joshua Warner
parent 7c24701d37
commit 6b889b1d78
7 changed files with 108 additions and 102 deletions
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10
include/avian/codegen/registers.h
View File

@ -16,11 +16,13 @@
namespace avian { namespace avian {
namespace codegen { namespace codegen {
class RegisterMask;
class Register { class Register {
private: private:
int8_t index; int8_t index;
public: public:
constexpr Register(int8_t index) : index(index) {} explicit constexpr Register(int8_t index) : index(index) {}
constexpr Register() : index(-1) {} constexpr Register() : index(-1) {}
constexpr bool operator == (Register o) const { constexpr bool operator == (Register o) const {
@ -31,6 +33,8 @@ public:
return !(*this == o); return !(*this == o);
} }
constexpr RegisterMask operator | (Register o) const;
constexpr operator int8_t() const { constexpr operator int8_t() const {
return index; return index;
} }
@ -87,6 +91,10 @@ public:
static RegisterMask None; static RegisterMask None;
}; };
constexpr RegisterMask Register::operator | (Register o) const {
return RegisterMask(*this) | o;
}
class BoundedRegisterMask { class BoundedRegisterMask {
public: public:
RegisterMask mask; RegisterMask mask;

12
src/codegen/target/arm/assembler.cpp
View File

@ -166,7 +166,7 @@ class MyArchitecture : public Architecture {
virtual Register scratch() virtual Register scratch()
{ {
return 5; return Register(5);
} }
virtual Register stack() virtual Register stack()
@ -181,22 +181,22 @@ class MyArchitecture : public Architecture {
virtual Register returnLow() virtual Register returnLow()
{ {
return 0; return Register(0);
} }
virtual Register returnHigh() virtual Register returnHigh()
{ {
return 1; return Register(1);
} }
virtual Register virtualCallTarget() virtual Register virtualCallTarget()
{ {
return 4; return Register(4);
} }
virtual Register virtualCallIndex() virtual Register virtualCallIndex()
{ {
return 3; return Register(3);
} }
virtual ir::TargetInfo targetInfo() virtual ir::TargetInfo targetInfo()
@ -265,7 +265,7 @@ class MyArchitecture : public Architecture {
{ {
assertT(&con, index < argumentRegisterCount()); assertT(&con, index < argumentRegisterCount());
return index; return Register(index);
} }
virtual bool hasLinkRegister() virtual bool hasLinkRegister()

116
src/codegen/target/arm/encode.h
View File

@ -135,11 +135,11 @@ inline int XFER2I(int cond,
} }
inline int COOP(int cond, inline int COOP(int cond,
int opcode_1, int opcode_1,
Register CRn, int CRn,
Register CRd, int CRd,
int cp_num, int cp_num,
int opcode_2, int opcode_2,
Register CRm) int CRm)
{ {
return cond << 28 | 0xe << 24 | opcode_1 << 20 | (int8_t)CRn << 16 | (int8_t)CRd << 12 return cond << 28 | 0xe << 24 | opcode_1 << 20 | (int8_t)CRn << 16 | (int8_t)CRd << 12
| cp_num << 8 | opcode_2 << 5 | (int8_t)CRm; | cp_num << 8 | opcode_2 << 5 | (int8_t)CRm;
@ -151,7 +151,7 @@ inline int COXFER(int cond,
int W, int W,
int L, int L,
Register Rn, Register Rn,
Register CRd, int CRd,
int cp_num, int cp_num,
int offset) // offset is in words, not bytes int offset) // offset is in words, not bytes
{ {
@ -161,17 +161,17 @@ inline int COXFER(int cond,
inline int COREG(int cond, inline int COREG(int cond,
int opcode_1, int opcode_1,
int L, int L,
Register CRn, int CRn,
Register Rd, Register Rd,
int cp_num, int cp_num,
int opcode_2, int opcode_2,
Register CRm) int CRm)
{ {
return cond << 28 | 0xe << 24 | opcode_1 << 21 | L << 20 | (int8_t)CRn << 16 return cond << 28 | 0xe << 24 | opcode_1 << 21 | L << 20 | (int8_t)CRn << 16
| (int8_t)Rd << 12 | cp_num << 8 | opcode_2 << 5 | 1 << 4 | (int8_t)CRm; | (int8_t)Rd << 12 | cp_num << 8 | opcode_2 << 5 | 1 << 4 | (int8_t)CRm;
} }
inline int inline int
COREG2(int cond, int L, Register Rn, Register Rd, int cp_num, int opcode, Register CRm) COREG2(int cond, int L, Register Rn, Register Rd, int cp_num, int opcode, int CRm)
{ {
return cond << 28 | 0xc4 << 20 | L << 20 | (int8_t)Rn << 16 | (int8_t)Rd << 12 | cp_num << 8 return cond << 28 | 0xc4 << 20 | L << 20 | (int8_t)Rn << 16 | (int8_t)Rd << 12 | cp_num << 8
| opcode << 4 | (int8_t)CRm; | opcode << 4 | (int8_t)CRm;
@ -225,7 +225,7 @@ inline int rsc(Register Rd, Register Rn, Register Rm, int Sh = 0, int shift = 0)
} }
inline int cmp(Register Rn, Register Rm, int Sh = 0, int shift = 0) inline int cmp(Register Rn, Register Rm, int Sh = 0, int shift = 0)
{ {
return DATA(AL, 0xa, 1, Rn, 0, shift, Sh, Rm); return DATA(AL, 0xa, 1, Rn, Register(0), shift, Sh, Rm);
} }
inline int orr(Register Rd, Register Rn, Register Rm, int Sh = 0, int shift = 0) inline int orr(Register Rd, Register Rn, Register Rm, int Sh = 0, int shift = 0)
{ {
@ -233,11 +233,11 @@ inline int orr(Register Rd, Register Rn, Register Rm, int Sh = 0, int shift = 0)
} }
inline int mov(Register Rd, Register Rm, int Sh = 0, int shift = 0) inline int mov(Register Rd, Register Rm, int Sh = 0, int shift = 0)
{ {
return DATA(AL, 0xd, 0, 0, Rd, shift, Sh, Rm); return DATA(AL, 0xd, 0, Register(0), Rd, shift, Sh, Rm);
} }
inline int mvn(Register Rd, Register Rm, int Sh = 0, int shift = 0) inline int mvn(Register Rd, Register Rm, int Sh = 0, int shift = 0)
{ {
return DATA(AL, 0xf, 0, 0, Rd, shift, Sh, Rm); return DATA(AL, 0xf, 0, Register(0), Rd, shift, Sh, Rm);
} }
inline int andi(Register Rd, Register Rn, int imm, int rot = 0) inline int andi(Register Rd, Register Rn, int imm, int rot = 0)
{ {
@ -265,11 +265,11 @@ inline int bici(Register Rd, Register Rn, int imm, int rot = 0)
} }
inline int cmpi(Register Rn, int imm, int rot = 0) inline int cmpi(Register Rn, int imm, int rot = 0)
{ {
return DATAI(AL, 0xa, 1, Rn, 0, rot, imm); return DATAI(AL, 0xa, 1, Rn, Register(0), rot, imm);
} }
inline int movi(Register Rd, int imm, int rot = 0) inline int movi(Register Rd, int imm, int rot = 0)
{ {
return DATAI(AL, 0xd, 0, 0, Rd, rot, imm); return DATAI(AL, 0xd, 0, Register(0), Rd, rot, imm);
} }
inline int orrsh(Register Rd, Register Rn, Register Rm, Register Rs, int Sh) inline int orrsh(Register Rd, Register Rn, Register Rm, Register Rs, int Sh)
{ {
@ -277,11 +277,11 @@ inline int orrsh(Register Rd, Register Rn, Register Rm, Register Rs, int Sh)
} }
inline int movsh(Register Rd, Register Rm, Register Rs, int Sh) inline int movsh(Register Rd, Register Rm, Register Rs, int Sh)
{ {
return DATAS(AL, 0xd, 0, 0, Rd, Rs, Sh, Rm); return DATAS(AL, 0xd, 0, Register(0), Rd, Rs, Sh, Rm);
} }
inline int mul(Register Rd, Register Rm, Register Rs) inline int mul(Register Rd, Register Rm, Register Rs)
{ {
return MULTIPLY(AL, 0, 0, Rd, 0, Rs, Rm); return MULTIPLY(AL, 0, 0, Rd, Register(0), Rs, Rm);
} }
inline int mla(Register Rd, Register Rm, Register Rs, Register Rn) inline int mla(Register Rd, Register Rm, Register Rs, Register Rn)
{ {
@ -404,31 +404,31 @@ inline int bkpt(int16_t immed)
inline int mcr(int coproc, inline int mcr(int coproc,
int opcode_1, int opcode_1,
Register Rd, Register Rd,
Register CRn, int CRn,
Register CRm, int CRm,
int opcode_2 = 0) int opcode_2 = 0)
{ {
return COREG(AL, opcode_1, 0, CRn, Rd, coproc, opcode_2, CRm); return COREG(AL, opcode_1, 0, CRn, Rd, coproc, opcode_2, CRm);
} }
inline int mcrr(int coproc, int opcode, Register Rd, Register Rn, Register CRm) inline int mcrr(int coproc, int opcode, Register Rd, Register Rn, int CRm)
{ {
return COREG2(AL, 0, Rn, Rd, coproc, opcode, CRm); return COREG2(AL, 0, Rn, Rd, coproc, opcode, CRm);
} }
inline int mrc(int coproc, inline int mrc(int coproc,
int opcode_1, int opcode_1,
Register Rd, Register Rd,
Register CRn, int CRn,
Register CRm, int CRm,
int opcode_2 = 0) int opcode_2 = 0)
{ {
return COREG(AL, opcode_1, 1, CRn, Rd, coproc, opcode_2, CRm); return COREG(AL, opcode_1, 1, CRn, Rd, coproc, opcode_2, CRm);
} }
inline int mrrc(int coproc, int opcode, Register Rd, Register Rn, Register CRm) inline int mrrc(int coproc, int opcode, Register Rd, Register Rn, int CRm)
{ {
return COREG2(AL, 1, Rn, Rd, coproc, opcode, CRm); return COREG2(AL, 1, Rn, Rd, coproc, opcode, CRm);
} }
// VFP FLOATING-POINT INSTRUCTIONS // VFP FLOATING-POINT INSTRUCTIONS
inline int fmuls(Register Sd, Register Sn, Register Sm) inline int fmuls(int Sd, int Sn, int Sm)
{ {
return COOP(AL, return COOP(AL,
((int8_t)Sd & 1) << 2 | 2, ((int8_t)Sd & 1) << 2 | 2,
@ -438,7 +438,7 @@ inline int fmuls(Register Sd, Register Sn, Register Sm)
((int8_t)Sn & 1) << 2 | ((int8_t)Sm & 1), ((int8_t)Sn & 1) << 2 | ((int8_t)Sm & 1),
(int8_t)Sm >> 1); (int8_t)Sm >> 1);
} }
inline int fadds(Register Sd, Register Sn, Register Sm) inline int fadds(int Sd, int Sn, int Sm)
{ {
return COOP(AL, return COOP(AL,
((int8_t)Sd & 1) << 2 | 3, ((int8_t)Sd & 1) << 2 | 3,
@ -448,7 +448,7 @@ inline int fadds(Register Sd, Register Sn, Register Sm)
((int8_t)Sn & 1) << 2 | ((int8_t)Sm & 1), ((int8_t)Sn & 1) << 2 | ((int8_t)Sm & 1),
(int8_t)Sm >> 1); (int8_t)Sm >> 1);
} }
inline int fsubs(Register Sd, Register Sn, Register Sm) inline int fsubs(int Sd, int Sn, int Sm)
{ {
return COOP(AL, return COOP(AL,
((int8_t)Sd & 1) << 2 | 3, ((int8_t)Sd & 1) << 2 | 3,
@ -458,7 +458,7 @@ inline int fsubs(Register Sd, Register Sn, Register Sm)
((int8_t)Sn & 1) << 2 | ((int8_t)Sm & 1) | 2, ((int8_t)Sn & 1) << 2 | ((int8_t)Sm & 1) | 2,
(int8_t)Sm >> 1); (int8_t)Sm >> 1);
} }
inline int fdivs(Register Sd, Register Sn, Register Sm) inline int fdivs(int Sd, int Sn, int Sm)
{ {
return COOP(AL, return COOP(AL,
((int8_t)Sd & 1) << 2 | 8, ((int8_t)Sd & 1) << 2 | 8,
@ -484,37 +484,37 @@ inline int fdivd(int Dd, int Dn, int Dm)
{ {
return COOP(AL, 8, Dn, Dd, 11, 0, Dm); return COOP(AL, 8, Dn, Dd, 11, 0, Dm);
} }
inline int fcpys(Register Sd, Register Sm) inline int fcpys(int Sd, int Sm)
{ {
return COOP(AL, 0xb | ((int8_t)Sd & 1) << 2, 0, (int8_t)Sd >> 1, 10, 2 | ((int8_t)Sm & 1), (int8_t)Sm >> 1); return COOP(AL, 0xb | (Sd & 1) << 2, 0, Sd >> 1, 10, 2 | (Sm & 1), Sm >> 1);
} }
inline int fabss(Register Sd, Register Sm) inline int fabss(int Sd, int Sm)
{ {
return COOP(AL, 0xb | ((int8_t)Sd & 1) << 2, 0, (int8_t)Sd >> 1, 10, 6 | ((int8_t)Sm & 1), (int8_t)Sm >> 1); return COOP(AL, 0xb | (Sd & 1) << 2, 0, Sd >> 1, 10, 6 | (Sm & 1), Sm >> 1);
} }
inline int fnegs(Register Sd, Register Sm) inline int fnegs(int Sd, int Sm)
{ {
return COOP(AL, 0xb | ((int8_t)Sd & 1) << 2, 1, (int8_t)Sd >> 1, 10, 2 | ((int8_t)Sm & 1), (int8_t)Sm >> 1); return COOP(AL, 0xb | (Sd & 1) << 2, 1, Sd >> 1, 10, 2 | (Sm & 1), Sm >> 1);
} }
inline int fsqrts(Register Sd, Register Sm) inline int fsqrts(int Sd, int Sm)
{ {
return COOP(AL, 0xb | ((int8_t)Sd & 1) << 2, 1, (int8_t)Sd >> 1, 10, 6 | ((int8_t)Sm & 1), (int8_t)Sm >> 1); return COOP(AL, 0xb | (Sd & 1) << 2, 1, Sd >> 1, 10, 6 | (Sm & 1), Sm >> 1);
} }
inline int fcmps(Register Sd, Register Sm) inline int fcmps(int Sd, int Sm)
{ {
return COOP(AL, 0xb | ((int8_t)Sd & 1) << 2, 4, (int8_t)Sd >> 1, 10, 2 | ((int8_t)Sm & 1), (int8_t)Sm >> 1); return COOP(AL, 0xb | (Sd & 1) << 2, 4, Sd >> 1, 10, 2 | (Sm & 1), Sm >> 1);
} }
inline int fcvtds(int Dd, Register Sm) inline int fcvtds(int Dd, int Sm)
{ {
return COOP(AL, 0xb, 7, Dd, 10, 6 | ((int8_t)Sm & 1), (int8_t)Sm >> 1); return COOP(AL, 0xb, 7, Dd, 10, 6 | (Sm & 1), Sm >> 1);
} }
inline int fsitos(Register Sd, Register Sm) inline int fsitos(int Sd, int Sm)
{ {
return COOP(AL, 0xb | ((int8_t)Sd & 1) << 2, 8, (int8_t)Sd >> 1, 10, 6 | ((int8_t)Sm & 1), (int8_t)Sm >> 1); return COOP(AL, 0xb | (Sd & 1) << 2, 8, Sd >> 1, 10, 6 | (Sm & 1), Sm >> 1);
} }
inline int ftosizs(Register Sd, Register Sm) inline int ftosizs(int Sd, int Sm)
{ {
return COOP(AL, 0xb | ((int8_t)Sd & 1) << 2, 0xd, (int8_t)Sd >> 1, 10, 6 | ((int8_t)Sm & 1), (int8_t)Sm >> 1); return COOP(AL, 0xb | (Sd & 1) << 2, 0xd, Sd >> 1, 10, 6 | (Sm & 1), Sm >> 1);
} }
inline int fcpyd(int Dd, int Dm) inline int fcpyd(int Dd, int Dm)
{ {
@ -538,43 +538,43 @@ inline int fcmpd(int Dd, int Dm)
return COOP(AL, 0xb, 4, Dd, 11, 2, Dm); return COOP(AL, 0xb, 4, Dd, 11, 2, Dm);
} }
// double-precision conversion instructions // double-precision conversion instructions
inline int fcvtsd(Register Sd, int Dm) inline int fcvtsd(int Sd, int Dm)
{ {
return COOP(AL, 0xb | ((int8_t)Sd & 1) << 2, 7, (int8_t)Sd >> 1, 11, 6, Dm); return COOP(AL, 0xb | (Sd & 1) << 2, 7, Sd >> 1, 11, 6, Dm);
} }
inline int fsitod(Register Dd, Register Sm) inline int fsitod(int Dd, int Sm)
{ {
return COOP(AL, 0xb, 8, Dd, 11, 6 | ((int8_t)Sm & 1), (int8_t)Sm >> 1); return COOP(AL, 0xb, 8, Dd, 11, 6 | (Sm & 1), Sm >> 1);
} }
inline int ftosizd(Register Sd, Register Dm) inline int ftosizd(int Sd, int Dm)
{ {
return COOP(AL, 0xb | ((int8_t)Sd & 1) << 2, 0xd, (int8_t)Sd >> 1, 11, 6, Dm); return COOP(AL, 0xb | (Sd & 1) << 2, 0xd, Sd >> 1, 11, 6, Dm);
} }
// single load/store instructions for both precision types // single load/store instructions for both precision types
inline int flds(Register Sd, Register Rn, int offset = 0) inline int flds(int Sd, Register Rn, int offset = 0)
{ {
return COXFER(AL, 1, 1, (int8_t)Sd & 1, 0, 1, Rn, (int8_t)Sd >> 1, 10, offset); return COXFER(AL, 1, 1, Sd & 1, 0, 1, Rn, Sd >> 1, 10, offset);
}; };
inline int fldd(Register Dd, Register Rn, int offset = 0) inline int fldd(int Dd, Register Rn, int offset = 0)
{ {
return COXFER(AL, 1, 1, 0, 0, 1, Rn, Dd, 11, offset); return COXFER(AL, 1, 1, 0, 0, 1, Rn, Dd, 11, offset);
}; };
inline int fsts(Register Sd, Register Rn, int offset = 0) inline int fsts(int Sd, Register Rn, int offset = 0)
{ {
return COXFER(AL, 1, 1, (int8_t)Sd & 1, 0, 0, Rn, (int8_t)Sd >> 1, 10, offset); return COXFER(AL, 1, 1, Sd & 1, 0, 0, Rn, Sd >> 1, 10, offset);
}; };
inline int fstd(Register Dd, Register Rn, int offset = 0) inline int fstd(int Dd, Register Rn, int offset = 0)
{ {
return COXFER(AL, 1, 1, 0, 0, 0, Rn, Dd, 11, offset); return COXFER(AL, 1, 1, 0, 0, 0, Rn, Dd, 11, offset);
}; };
// move between GPRs and FPRs // move between GPRs and FPRs
inline int fmsr(Register Sn, Register Rd) inline int fmsr(int Sn, Register Rd)
{ {
return mcr(10, 0, Rd, (int8_t)Sn >> 1, 0, ((int8_t)Sn & 1) << 2); return mcr(10, 0, Rd, Sn >> 1, 0, (Sn & 1) << 2);
} }
inline int fmrs(Register Rd, Register Sn) inline int fmrs(Register Rd, int Sn)
{ {
return mrc(10, 0, Rd, (int8_t)Sn >> 1, 0, ((int8_t)Sn & 1) << 2); return mrc(10, 0, Rd, Sn >> 1, 0, (Sn & 1) << 2);
} }
// move to/from VFP system registers // move to/from VFP system registers
inline int fmrx(Register Rd, int reg) inline int fmrx(Register Rd, int reg)
@ -582,7 +582,7 @@ inline int fmrx(Register Rd, int reg)
return mrc(10, 7, Rd, reg, 0); return mrc(10, 7, Rd, reg, 0);
} }
// these move around pairs of single-precision registers // these move around pairs of single-precision registers
inline int fmdrr(Register Dm, Register Rd, Register Rn) inline int fmdrr(int Dm, Register Rd, Register Rn)
{ {
return mcrr(11, 1, Rd, Rn, Dm); return mcrr(11, 1, Rd, Rn, Dm);
} }
@ -670,7 +670,7 @@ inline int bpl(int offset)
} }
inline int fmstat() inline int fmstat()
{ {
return fmrx(15, FPSCR); return fmrx(Register(15), FPSCR);
} }
// todo: make this pretty: // todo: make this pretty:
inline int dmb() inline int dmb()

8
src/codegen/target/arm/operations.cpp
View File

@ -575,7 +575,7 @@ void float2IntRR(Context* con,
lir::RegisterPair* b) lir::RegisterPair* b)
{ {
Register tmp = newTemp(con, FPR_MASK); Register tmp = newTemp(con, FPR_MASK);
Register ftmp = fpr32(tmp); int ftmp = fpr32(tmp);
if (size == 8) { // double to int if (size == 8) { // double to int
emit(con, ftosizd(ftmp, fpr64(a))); emit(con, ftosizd(ftmp, fpr64(a)));
} else { // float to int } else { // float to int
@ -1129,7 +1129,7 @@ void moveAR2(Context* con,
lir::Constant constant(src->address); lir::Constant constant(src->address);
moveCR(con, srcSize, &constant, dstSize, dst); moveCR(con, srcSize, &constant, dstSize, dst);
lir::Memory memory(dst->low, 0, -1, 0); lir::Memory memory(dst->low, 0, NoRegister, 0);
moveMR(con, dstSize, &memory, dstSize, dst); moveMR(con, dstSize, &memory, dstSize, dst);
} }
@ -1491,7 +1491,7 @@ void longCallC(Context* con, unsigned size UNUSED, lir::Constant* target)
{ {
assertT(con, size == vm::TargetBytesPerWord); assertT(con, size == vm::TargetBytesPerWord);
lir::RegisterPair tmp(4); lir::RegisterPair tmp(Register(4));
moveCR2(con, vm::TargetBytesPerWord, target, &tmp, offsetPromise(con)); moveCR2(con, vm::TargetBytesPerWord, target, &tmp, offsetPromise(con));
callR(con, vm::TargetBytesPerWord, &tmp); callR(con, vm::TargetBytesPerWord, &tmp);
} }
@ -1500,7 +1500,7 @@ void longJumpC(Context* con, unsigned size UNUSED, lir::Constant* target)
{ {
assertT(con, size == vm::TargetBytesPerWord); assertT(con, size == vm::TargetBytesPerWord);
lir::RegisterPair tmp(4); // a non-arg reg that we don't mind clobbering lir::RegisterPair tmp(Register(4)); // a non-arg reg that we don't mind clobbering
moveCR2(con, vm::TargetBytesPerWord, target, &tmp, offsetPromise(con)); moveCR2(con, vm::TargetBytesPerWord, target, &tmp, offsetPromise(con));
jumpR(con, vm::TargetBytesPerWord, &tmp); jumpR(con, vm::TargetBytesPerWord, &tmp);
} }

16
src/codegen/target/arm/registers.h
View File

@ -49,15 +49,15 @@ inline int fpr32(lir::RegisterPair* reg)
} }
#ifdef ARCH_arm64 #ifdef ARCH_arm64
const int ThreadRegister = 19; constexpr Register ThreadRegister(19);
const int StackRegister = 31; constexpr Register StackRegister(31);
const int LinkRegister = 30; constexpr Register LinkRegister(30);
const int ProgramCounter = 0xFF; // i.e. unaddressable constexpr Register ProgramCounter(0xFE); // i.e. unaddressable
#else #else
const int ThreadRegister = 8; constexpr Register ThreadRegister(8);
const int StackRegister = 13; constexpr Register StackRegister(13);
const int LinkRegister = 14; constexpr Register LinkRegister(14);
const int ProgramCounter = 15; constexpr Register ProgramCounter(15);
#endif #endif
} // namespace arm } // namespace arm

34
src/codegen/target/x86/assembler.cpp
View File

@ -519,13 +519,13 @@ class MyArchitecture : public Architecture {
switch (op) { switch (op) {
case lir::Negate: case lir::Negate:
aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair); aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
aMask.setLowHighRegisterMasks(1 << rax, 1 << rdx); aMask.setLowHighRegisterMasks(rax, rdx);
break; break;
case lir::Absolute: case lir::Absolute:
if (aSize <= TargetBytesPerWord) { if (aSize <= TargetBytesPerWord) {
aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair); aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
aMask.setLowHighRegisterMasks(1 << rax, 0); aMask.setLowHighRegisterMasks(rax, 0);
} else { } else {
*thunk = true; *thunk = true;
} }
@ -603,13 +603,12 @@ class MyArchitecture : public Architecture {
aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair) aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair)
| (1 << (unsigned)lir::Operand::Type::Memory); | (1 << (unsigned)lir::Operand::Type::Memory);
const RegisterMask mask = GeneralRegisterMask const RegisterMask mask = GeneralRegisterMask
& ~((1 << rax) | (1 << rdx)); .excluding(rax).excluding(rdx);
aMask.setLowHighRegisterMasks(mask, mask); aMask.setLowHighRegisterMasks(mask, mask);
} else if (aSize == 1 or bSize == 1) { } else if (aSize == 1 or bSize == 1) {
aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair) aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair)
| (1 << (unsigned)lir::Operand::Type::Memory); | (1 << (unsigned)lir::Operand::Type::Memory);
const RegisterMask mask = (1 << rax) | (1 << rcx) | (1 << rdx) const RegisterMask mask = rax | rcx | rdx | rbx;
| (1 << rbx);
aMask.setLowHighRegisterMasks(mask, mask); aMask.setLowHighRegisterMasks(mask, mask);
} }
} }
@ -632,7 +631,7 @@ class MyArchitecture : public Architecture {
switch (op) { switch (op) {
case lir::Absolute: case lir::Absolute:
bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair); bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
bMask.setLowHighRegisterMasks(1 << rax, 0); bMask.setLowHighRegisterMasks(rax, 0);
break; break;
case lir::FloatAbsolute: case lir::FloatAbsolute:
@ -679,10 +678,9 @@ class MyArchitecture : public Architecture {
if (TargetBytesPerWord == 4) { if (TargetBytesPerWord == 4) {
if (aSize == 4 and bSize == 8) { if (aSize == 4 and bSize == 8) {
bMask.setLowHighRegisterMasks(1 << rax, 1 << rdx); bMask.setLowHighRegisterMasks(rax, rdx);
} else if (aSize == 1 or bSize == 1) { } else if (aSize == 1 or bSize == 1) {
const RegisterMask mask = (1 << rax) | (1 << rcx) | (1 << rdx) const RegisterMask mask = rax | rcx | rdx | rbx;
| (1 << rbx);
bMask.setLowHighRegisterMasks(mask, mask); bMask.setLowHighRegisterMasks(mask, mask);
} }
} }
@ -775,9 +773,9 @@ class MyArchitecture : public Architecture {
case lir::Multiply: case lir::Multiply:
if (TargetBytesPerWord == 4 and aSize == 8) { if (TargetBytesPerWord == 4 and aSize == 8) {
const RegisterMask mask = GeneralRegisterMask & ~((1 << rax) | (1 << rdx)); const RegisterMask mask = GeneralRegisterMask .excluding(rax).excluding(rdx);
aMask.setLowHighRegisterMasks(mask, mask); aMask.setLowHighRegisterMasks(mask, mask);
bMask.setLowHighRegisterMasks(mask, 1 << rdx); bMask.setLowHighRegisterMasks(mask, rdx);
} else { } else {
aMask.setLowHighRegisterMasks(GeneralRegisterMask, 0); aMask.setLowHighRegisterMasks(GeneralRegisterMask, 0);
bMask.setLowHighRegisterMasks(GeneralRegisterMask, 0); bMask.setLowHighRegisterMasks(GeneralRegisterMask, 0);
@ -789,8 +787,8 @@ class MyArchitecture : public Architecture {
*thunk = true; *thunk = true;
} else { } else {
aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair); aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
aMask.setLowHighRegisterMasks(GeneralRegisterMask & ~((1 << rax) | (1 << rdx)), 0); aMask.setLowHighRegisterMasks(GeneralRegisterMask .excluding(rax).excluding(rdx), 0);
bMask.setLowHighRegisterMasks(1 << rax, 0); bMask.setLowHighRegisterMasks(rax, 0);
} }
break; break;
@ -799,8 +797,8 @@ class MyArchitecture : public Architecture {
*thunk = true; *thunk = true;
} else { } else {
aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair); aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
aMask.setLowHighRegisterMasks(GeneralRegisterMask & ~((1 << rax) | (1 << rdx)), 0); aMask.setLowHighRegisterMasks(GeneralRegisterMask .excluding(rax).excluding(rdx), 0);
bMask.setLowHighRegisterMasks(1 << rax, 0); bMask.setLowHighRegisterMasks(rax, 0);
} }
break; break;
@ -808,12 +806,12 @@ class MyArchitecture : public Architecture {
case lir::ShiftRight: case lir::ShiftRight:
case lir::UnsignedShiftRight: { case lir::UnsignedShiftRight: {
if (TargetBytesPerWord == 4 and bSize == 8) { if (TargetBytesPerWord == 4 and bSize == 8) {
const RegisterMask mask = GeneralRegisterMask & ~(1 << rcx); const RegisterMask mask = GeneralRegisterMask.excluding(rcx);
aMask.setLowHighRegisterMasks(mask, mask); aMask.setLowHighRegisterMasks(mask, mask);
bMask.setLowHighRegisterMasks(mask, mask); bMask.setLowHighRegisterMasks(mask, mask);
} else { } else {
aMask.setLowHighRegisterMasks(static_cast<uint64_t>(1) << rcx, GeneralRegisterMask); aMask.setLowHighRegisterMasks(rcx, GeneralRegisterMask);
const RegisterMask mask = GeneralRegisterMask & ~(1 << rcx); const RegisterMask mask = GeneralRegisterMask.excluding(rcx);
bMask.setLowHighRegisterMasks(mask, mask); bMask.setLowHighRegisterMasks(mask, mask);
} }
} break; } break;

14
src/codegen/target/x86/operations.cpp
View File

@ -491,7 +491,7 @@ void moveAR(Context* c,
assertT(c, vm::TargetBytesPerWord == 8 or (aSize == 4 and bSize == 4)); assertT(c, vm::TargetBytesPerWord == 8 or (aSize == 4 and bSize == 4));
lir::Constant constant(a->address); lir::Constant constant(a->address);
lir::Memory memory(b->low, 0, -1, 0); lir::Memory memory(b->low, 0, NoRegister, 0);
moveCR(c, aSize, &constant, bSize, b); moveCR(c, aSize, &constant, bSize, b);
moveMR(c, bSize, &memory, bSize, b); moveMR(c, bSize, &memory, bSize, b);
@ -507,7 +507,7 @@ void moveCM(Context* c,
case 1: case 1:
maybeRex(c, bSize, b); maybeRex(c, bSize, b);
opcode(c, 0xc6); opcode(c, 0xc6);
modrmSibImm(c, 0, b->scale, b->index, b->base, b->offset); modrmSibImm(c, rax, b->scale, b->index, b->base, b->offset);
c->code.append(a->value->value()); c->code.append(a->value->value());
break; break;
@ -515,14 +515,14 @@ void moveCM(Context* c,
opcode(c, 0x66); opcode(c, 0x66);
maybeRex(c, bSize, b); maybeRex(c, bSize, b);
opcode(c, 0xc7); opcode(c, 0xc7);
modrmSibImm(c, 0, b->scale, b->index, b->base, b->offset); modrmSibImm(c, rax, b->scale, b->index, b->base, b->offset);
c->code.append2(a->value->value()); c->code.append2(a->value->value());
break; break;
case 4: case 4:
maybeRex(c, bSize, b); maybeRex(c, bSize, b);
opcode(c, 0xc7); opcode(c, 0xc7);
modrmSibImm(c, 0, b->scale, b->index, b->base, b->offset); modrmSibImm(c, rax, b->scale, b->index, b->base, b->offset);
if (a->value->resolved()) { if (a->value->resolved()) {
c->code.append4(a->value->value()); c->code.append4(a->value->value());
} else { } else {
@ -536,7 +536,7 @@ void moveCM(Context* c,
if (a->value->resolved() and vm::fitsInInt32(a->value->value())) { if (a->value->resolved() and vm::fitsInInt32(a->value->value())) {
maybeRex(c, bSize, b); maybeRex(c, bSize, b);
opcode(c, 0xc7); opcode(c, 0xc7);
modrmSibImm(c, 0, b->scale, b->index, b->base, b->offset); modrmSibImm(c, rax, b->scale, b->index, b->base, b->offset);
c->code.append4(a->value->value()); c->code.append4(a->value->value());
} else { } else {
lir::RegisterPair tmp(c->client->acquireTemporary(GeneralRegisterMask)); lir::RegisterPair tmp(c->client->acquireTemporary(GeneralRegisterMask));
@ -970,10 +970,10 @@ void multiplyRR(Context* c,
lir::RegisterPair ah(a->high); lir::RegisterPair ah(a->high);
lir::RegisterPair bh(b->high); lir::RegisterPair bh(b->high);
lir::RegisterPair tmp(-1); lir::RegisterPair tmp(NoRegister);
lir::RegisterPair* scratch; lir::RegisterPair* scratch;
if (a->low == b->low) { if (a->low == b->low) {
tmp.low = c->client->acquireTemporary(GeneralRegisterMask & ~(1 << rax)); tmp.low = c->client->acquireTemporary(GeneralRegisterMask.excluding(rax));
scratch = &tmp; scratch = &tmp;
moveRR(c, 4, b, 4, scratch); moveRR(c, 4, b, 4, scratch);
} else { } else {