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https://github.com/corda/corda.git
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prelim 64-bit mult and shift support
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JET
parent
8ecd6a0394
commit
5a08062190
151
src/powerpc.cpp
Normal file → Executable file
151
src/powerpc.cpp
Normal file → Executable file
@ -73,6 +73,7 @@ inline int addis(int rt, int ra, int i) { return D(15, rt, ra, i); }
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inline int subf(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 40, 0); }
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inline int subfc(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 8, 0); }
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inline int subfe(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 136, 0); }
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inline int subfic(int rt, int ra, int i) { return D(8, rt, ra, ri); }
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inline int mullw(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 235, 0); }
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inline int mulhw(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 75, 0); }
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inline int mulhwu(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 11, 0); }
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@ -393,7 +394,14 @@ inline int H(Reg* r) { return r->high; }
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void shiftLeftR(Context* con, unsigned size, Reg* a, Reg* b, Reg* t)
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{
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if(size == 8) {
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abort(con); // todo
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issue(con, subfic(31, R(a), 32));
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issue(con, slw(R(b), R(b), R(a)));
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issue(con, srw(0, H(b), 31));
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issue(con, or_(R(b), R(b), 0));
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issue(con, addi(31, R(a), -32));
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issue(con, slw(0, H(b), 31));
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issue(con, or_(R(b), R(b), 0));
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issue(con, slw(H(b), H(b), R(a)));
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} else
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issue(con, slw(R(t), R(b), R(a)));
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}
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@ -585,7 +593,7 @@ void addR(Context* con, unsigned size, Reg* a, Reg* b, Reg* t) {
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}
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void addC(Context* con, unsigned size, Const* a, Reg* b, Reg* t) {
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assert(con, size == BytesPerWord);
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assert(con, size == 4);
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int32_t i = getVal(a);
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if(i) {
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@ -605,7 +613,7 @@ void subR(Context* con, unsigned size, Reg* a, Reg* b, Reg* t) {
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}
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void subC(Context* con, unsigned size, Const* a, Reg* b, Reg* t) {
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assert(con, size == BytesPerWord);
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assert(con, size == 4);
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int64_t i = getVal(a);
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if(i) {
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@ -617,26 +625,28 @@ void subC(Context* con, unsigned size, Const* a, Reg* b, Reg* t) {
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void multiplyR(Context* con, unsigned size, Reg* a, Reg* b, Reg* t) {
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if(size == 8) {
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if(BytesPerWord == 8) {
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// issue(con, mulld(R(t), R(a), R(b)));
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abort(con);
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} else {
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abort(con); // todo
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}
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Reg tmp(getTemp(con));
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issue(con, mullw(H(t), H(a), R(b)));
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issue(con, mullw(R(tmp), R(a), H(b)));
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issue(con, add(H(t), H(t), R(tmp)));
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issue(con, mulhw(R(tmp), R(a), R(b)));
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issue(con, add(H(t), H(t), R(tmp)));
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freeTemp(con, R(tmp));
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} else {
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issue(con, mullw(R(t), R(a), R(b)));
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}
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}
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void multiplyC(Context* con, unsigned size, Const* a, Reg* b, Reg* t) {
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assert(con, size == BytesPerWord);
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assert(con, size == 4);
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int64_t i = getVal(a);
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issue(con, mulli(R(t), R(b), i));
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}
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void divideR(Context* con, unsigned size, Reg* a, Reg* b, Reg* t) {
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if(size == 8 && BytesPerWord == 8) {
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issue(con, divd(R(t), R(b), R(a)));
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if(size == 8) {
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issue(con, 0);
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issue(con, 0);
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} else {
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issue(con, divw(R(t), R(b), R(a)));
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}
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@ -648,6 +658,33 @@ void remainderR(Context* con, unsigned size, Reg* a, Reg* b, Reg* t) {
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subR(con, size, t, a, t);
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}
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void andC(Context* c, unsigned size, Assembler::Constant* a,
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Assembler::Register* b, Assembler::Register* dst)
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{
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abort(c); // todo
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int64_t v = a->value->value();
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if(size == 8) {
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ResolvedPromise high((v >> 32) & 0xFFFFFFFF);
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Assembler::Constant ah(&high);
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ResolvedPromise low(v & 0xFFFFFFFF);
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Assembler::Constant al(&low);
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Assembler::Register bh(b->high);
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Assembler::Register dh(dst->high);
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andC(c, 4, &al, b, dst);
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andC(c, 4, &ah, &bh, &dh);
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} else {
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issue(c, andi(dst->low, b->low, v));
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if (v >> 16) {
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issue(c, andis(dst->low, b->low, v >> 16));
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}
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}
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}
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int
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normalize(Context* c, int offset, int index, unsigned scale,
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bool* preserveIndex)
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@ -882,90 +919,6 @@ moveCR(Context* c, unsigned srcSize, Assembler::Constant* src,
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// issue(con, ori(R(t), R(t), lo16(i)));
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// }
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void
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andR(Context* c, unsigned size, Assembler::Register* a,
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Assembler::Register* b, Assembler::Register* dst)
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{
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if (size == 8) {
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Assembler::Register ah(a->high);
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Assembler::Register bh(b->high);
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Assembler::Register dh(dst->high);
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andR(c, 4, a, b, dst);
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andR(c, 4, &ah, &bh, &dh);
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} else {
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issue(c, and_(dst->low, a->low, b->low));
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}
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}
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void
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andC(Context* c, unsigned size, Assembler::Constant* a,
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Assembler::Register* b, Assembler::Register* dst)
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{
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int64_t v = a->value->value();
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if (size == 8) {
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ResolvedPromise high((v >> 32) & 0xFFFFFFFF);
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Assembler::Constant ah(&high);
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ResolvedPromise low(v & 0xFFFFFFFF);
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Assembler::Constant al(&low);
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Assembler::Register bh(b->high);
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Assembler::Register dh(dst->high);
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andC(c, 4, &al, b, dst);
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andC(c, 4, &ah, &bh, &dh);
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} else {
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// bitmasks of the form regex 0*1*0* can be handled in a single
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// rlwinm instruction, hence the following:
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uint32_t v32 = static_cast<uint32_t>(v);
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unsigned state = 0;
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unsigned start;
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unsigned end = 31;
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for (unsigned i = 0; i < 32; ++i) {
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unsigned bit = (v32 >> i) & 1;
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switch (state) {
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case 0:
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if (bit) {
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start = i;
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state = 1;
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}
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break;
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case 1:
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if (bit == 0) {
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end = i - 1;
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state = 2;
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}
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break;
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case 2:
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if (bit) {
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// not in 0*1*0* form. We can only use andi(s) if either
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// the topmost or bottommost 16 bits are zero.
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if ((v32 >> 16) == 0) {
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issue(c, andi(dst->low, b->low, v32));
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} else if ((v32 & 0xFFFF) == 0) {
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issue(c, andis(dst->low, b->low, v32 >> 16));
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} else {
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moveCR(c, 4, a, 4, dst);
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andR(c, 4, b, dst, dst);
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}
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return;
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}
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break;
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}
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}
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if (state) {
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issue(c, rlwinm(dst->low, b->low, 0, 31 - end, 31 - start));
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}
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}
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}
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void
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moveAR(Context* c, unsigned srcSize, Assembler::Address* src,
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unsigned dstSize, Assembler::Register* dst)
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@ -1223,7 +1176,6 @@ populateTables(ArchitectureContext* c)
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to[index(Subtract, C)] = CAST3(subC);
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to[index(And, C)] = CAST3(andC);
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to[index(And, R)] = CAST3(andR);
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to[index(LongCompare, R)] = CAST3(longCompareR);
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}
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@ -1312,7 +1264,7 @@ class MyArchitecture: public Assembler::Architecture {
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}
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virtual unsigned frameReturnAddressSize() {
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return 0;
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return 1;
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}
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virtual unsigned frameFooterSize() {
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@ -1383,6 +1335,7 @@ class MyArchitecture: public Assembler::Architecture {
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switch (op) {
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case Add:
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case Subtract:
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case Multiply:
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if (BytesPerWord == 4 and aSize == 8) {
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*aTypeMask = *bTypeMask = (1 << RegisterOperand);
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}
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@ -1393,6 +1346,7 @@ class MyArchitecture: public Assembler::Architecture {
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break;
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case Divide:
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*aTypeMask = (1 << RegisterOperand);
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if (BytesPerWord == 4 and aSize == 8) {
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*bTypeMask = ~0;
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*thunk = true;
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@ -1400,6 +1354,7 @@ class MyArchitecture: public Assembler::Architecture {
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break;
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case Remainder:
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*aTypeMask = (1 << RegisterOperand);
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if (BytesPerWord == 4 and aSize == 8) {
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*bTypeMask = ~0;
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*thunk = true;
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