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more ARM64 bugfixes

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This commit is contained in:
Joel Dice 2014-12-29 08:02:37 -07:00
parent 67f5461d82
commit 3e2545e5a7
2 changed files with 11 additions and 9 deletions
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2
src/codegen/target/arm/assembler.cpp
View File

@ -582,7 +582,7 @@ class MyArchitecture : public Architecture {
case lir::FloatMultiply: case lir::FloatMultiply:
case lir::FloatDivide: case lir::FloatDivide:
if (vfpSupported()) { if (vfpSupported()) {
bMask.typeMask = lir::Operand::RegisterPairMask; aMask.typeMask = lir::Operand::RegisterPairMask;
aMask.setLowHighRegisterMasks(FPR_MASK, FPR_MASK); aMask.setLowHighRegisterMasks(FPR_MASK, FPR_MASK);
bMask = aMask; bMask = aMask;
} else { } else {

18
src/codegen/target/arm/operations64.cpp
View File

@ -259,9 +259,9 @@ uint32_t fcvtasWdSn(Register Rd, Register Fn)
return 0x1e240000 | (Fn.index() << 5) | Rd.index(); return 0x1e240000 | (Fn.index() << 5) | Rd.index();
} }
uint32_t scvtfDdWn(Register Fd, Register Rn) uint32_t scvtfDdXn(Register Fd, Register Rn)
{ {
return 0x1e620000 | (Rn.index() << 5) | Fd.index(); return 0x9e620000 | (Rn.index() << 5) | Fd.index();
} }
uint32_t scvtfSdWn(Register Fd, Register Rn) uint32_t scvtfSdWn(Register Fd, Register Rn)
@ -287,8 +287,8 @@ uint32_t strh(Register Rs, Register Rn, Register Rm)
uint32_t striFs(Register Fs, Register Rn, int offset, unsigned size) uint32_t striFs(Register Fs, Register Rn, int offset, unsigned size)
{ {
return (size == 8 ? 0xfc000000 : 0xbc000000) | (offset << 16) return (size == 8 ? 0xfd000000 : 0xbd000000)
| (Rn.index() << 5) | Fs.index(); | ((offset >> (size == 8 ? 3 : 2)) << 10) | (Rn.index() << 5) | Fs.index();
} }
uint32_t str(Register Rs, Register Rn, Register Rm, unsigned size) uint32_t str(Register Rs, Register Rn, Register Rm, unsigned size)
@ -352,8 +352,8 @@ uint32_t ldr(Register Rd, Register Rn, Register Rm, unsigned size)
uint32_t ldriFd(Register Fd, Register Rn, int offset, unsigned size) uint32_t ldriFd(Register Fd, Register Rn, int offset, unsigned size)
{ {
return (size == 8 ? 0xfc400000 : 0xbc400000) | (offset << 16) return (size == 8 ? 0xfd400000 : 0xbd400000)
| (Rn.index() << 5) | Fd.index(); | ((offset >> (size == 8 ? 3 : 2)) << 10) | (Rn.index() << 5) | Fd.index();
} }
uint32_t ldrbi(Register Rd, Register Rn, int offset) uint32_t ldrbi(Register Rd, Register Rn, int offset)
@ -808,9 +808,9 @@ void int2FloatRR(Context* c,
lir::RegisterPair* b) lir::RegisterPair* b)
{ {
if (size == 8) { if (size == 8) {
append(c, scvtfDdWn(fpr(a), b->low)); append(c, scvtfDdXn(fpr(b), a->low));
} else { } else {
append(c, scvtfSdWn(fpr(a), b->low)); append(c, scvtfSdWn(fpr(b), a->low));
} }
} }
@ -981,6 +981,7 @@ void store(Context* c,
switch (size) { switch (size) {
case 4: case 4:
case 8: case 8:
assertT(c, offset == (offset & (size == 8 ? (~7) : (~3))));
append(c, striFs(fpr(src->low), base, offset, size)); append(c, striFs(fpr(src->low), base, offset, size));
break; break;
@ -1119,6 +1120,7 @@ void load(Context* c,
switch (srcSize) { switch (srcSize) {
case 4: case 4:
case 8: case 8:
assertT(c, offset == (offset & (srcSize == 8 ? (~7) : (~3))));
append(c, ldriFd(fpr(dst->low), base, offset, srcSize)); append(c, ldriFd(fpr(dst->low), base, offset, srcSize));
break; break;