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more ARM64 bugfixes
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67f5461d82
commit
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@ -582,7 +582,7 @@ class MyArchitecture : public Architecture {
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case lir::FloatMultiply:
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case lir::FloatDivide:
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if (vfpSupported()) {
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bMask.typeMask = lir::Operand::RegisterPairMask;
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aMask.typeMask = lir::Operand::RegisterPairMask;
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aMask.setLowHighRegisterMasks(FPR_MASK, FPR_MASK);
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bMask = aMask;
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} else {
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@ -259,9 +259,9 @@ uint32_t fcvtasWdSn(Register Rd, Register Fn)
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return 0x1e240000 | (Fn.index() << 5) | Rd.index();
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}
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uint32_t scvtfDdWn(Register Fd, Register Rn)
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uint32_t scvtfDdXn(Register Fd, Register Rn)
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{
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return 0x1e620000 | (Rn.index() << 5) | Fd.index();
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return 0x9e620000 | (Rn.index() << 5) | Fd.index();
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}
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uint32_t scvtfSdWn(Register Fd, Register Rn)
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@ -287,8 +287,8 @@ uint32_t strh(Register Rs, Register Rn, Register Rm)
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uint32_t striFs(Register Fs, Register Rn, int offset, unsigned size)
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{
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return (size == 8 ? 0xfc000000 : 0xbc000000) | (offset << 16)
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| (Rn.index() << 5) | Fs.index();
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return (size == 8 ? 0xfd000000 : 0xbd000000)
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| ((offset >> (size == 8 ? 3 : 2)) << 10) | (Rn.index() << 5) | Fs.index();
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}
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uint32_t str(Register Rs, Register Rn, Register Rm, unsigned size)
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@ -352,8 +352,8 @@ uint32_t ldr(Register Rd, Register Rn, Register Rm, unsigned size)
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uint32_t ldriFd(Register Fd, Register Rn, int offset, unsigned size)
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{
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return (size == 8 ? 0xfc400000 : 0xbc400000) | (offset << 16)
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| (Rn.index() << 5) | Fd.index();
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return (size == 8 ? 0xfd400000 : 0xbd400000)
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| ((offset >> (size == 8 ? 3 : 2)) << 10) | (Rn.index() << 5) | Fd.index();
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}
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uint32_t ldrbi(Register Rd, Register Rn, int offset)
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@ -808,9 +808,9 @@ void int2FloatRR(Context* c,
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lir::RegisterPair* b)
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{
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if (size == 8) {
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append(c, scvtfDdWn(fpr(a), b->low));
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append(c, scvtfDdXn(fpr(b), a->low));
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} else {
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append(c, scvtfSdWn(fpr(a), b->low));
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append(c, scvtfSdWn(fpr(b), a->low));
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}
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}
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@ -981,6 +981,7 @@ void store(Context* c,
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switch (size) {
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case 4:
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case 8:
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assertT(c, offset == (offset & (size == 8 ? (~7) : (~3))));
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append(c, striFs(fpr(src->low), base, offset, size));
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break;
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@ -1119,6 +1120,7 @@ void load(Context* c,
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switch (srcSize) {
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case 4:
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case 8:
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assertT(c, offset == (offset & (srcSize == 8 ? (~7) : (~3))));
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append(c, ldriFd(fpr(dst->low), base, offset, srcSize));
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break;
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