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implement negateRR
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@ -68,6 +68,7 @@ inline int stwu(int rs, int ra, int i) { return D(37, rs, ra, i); }
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inline int stwx(int rs, int ra, int rb) { return X(31, rs, ra, rb, 151, 0); }
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inline int add(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 266, 0); }
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inline int addc(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 10, 0); }
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inline int addci(int rt, int ra, int i) { return D(12, rt, ra, i); }
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inline int adde(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 138, 0); }
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inline int addi(int rt, int ra, int i) { return D(14, rt, ra, i); }
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inline int addis(int rt, int ra, int i) { return D(15, rt, ra, i); }
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@ -83,6 +84,7 @@ inline int divw(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 491, 0);
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inline int divwu(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 459, 0); }
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inline int divd(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 489, 0); }
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inline int divdu(int rt, int ra, int rb) { return XO(31, rt, ra, rb, 0, 457, 0); }
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inline int neg(int rt, int ra) { return XO(31, rt, ra, 0, 0, 104, 0); }
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inline int and_(int rt, int ra, int rb) { return X(31, ra, rt, rb, 28, 0); }
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inline int andi(int rt, int ra, int i) { return D(28, ra, rt, i); }
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inline int andis(int rt, int ra, int i) { return D(29, ra, rt, i); }
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@ -1342,6 +1344,23 @@ moveCM(Context* c, unsigned srcSize, Assembler::Constant* src,
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}
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}
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void
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negateRR(Context* c, unsigned srcSize, Assembler::Register* src,
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unsigned dstSize, Assembler::Register* dst)
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{
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assert(c, srcSize == dstSize);
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if (srcSize == 8) {
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Assembler::Register dstHigh(dst->high);
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negateRR(c, 4, src, 4, dst);
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issue(c, addci(dst->high, dst->high, 0));
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negateRR(c, 4, &dstHigh, 4, &dstHigh);
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} else {
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issue(c, neg(dst->low, src->low));
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}
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}
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void
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callR(Context* c, unsigned size, Assembler::Register* target)
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{
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@ -1504,6 +1523,8 @@ populateTables(ArchitectureContext* c)
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bo[index(Compare, R, M)] = CAST2(compareRM);
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bo[index(Compare, C, M)] = CAST2(compareCM);
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bo[index(Negate, R, R)] = CAST2(negateRR);
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to[index(Add, R)] = CAST3(addR);
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to[index(Add, C)] = CAST3(addC);
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