mirror of
https://github.com/corda/corda.git
synced 2025-01-06 05:04:20 +00:00
single-precision hardfloat emission working
anything involving doubles (including conversions and thunking from singles) is still broken
This commit is contained in:
JET
parent
714aebfec1
commit
11d750af70
154
src/arm.cpp
154
src/arm.cpp
@ -57,8 +57,8 @@ inline int SWAP(int cond, int B, int Rn, int Rd, int Rm)
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{ return cond<<28 | 1<<24 | B<<22 | Rn<<16 | Rd<<12 | 9<<4 | Rm; }
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inline int COOP(int cond, int opcode_1, int CRn, int CRd, int cp_num, int opcode_2, int CRm)
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{ return cond<<28 | 0xe<<24 | opcode_1<<20 | CRn<<16 | CRd<<12 | cp_num<<8 | opcode_2<<5 | CRm; }
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inline int COXFER(int cond, int P, int U, int N, int W, int L, int Rn, int CRd, int cp_num, int offset)
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{ return cond<<28 | 0x6<<25 | P<<24 | U<<23 | N<<22 | W<<21 | L<<20 | Rn<<16 | CRd<<12 | cp_num<<8 | (offset&0xff); }
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inline int COXFER(int cond, int P, int U, int N, int W, int L, int Rn, int CRd, int cp_num, int offset) // offset is in words, not bytes
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{ return cond<<28 | 0x6<<25 | P<<24 | U<<23 | N<<22 | W<<21 | L<<20 | Rn<<16 | CRd<<12 | cp_num<<8 | (offset&0xff)>>2; }
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inline int COREG(int cond, int opcode_1, int L, int CRn, int Rd, int cp_num, int opcode_2, int CRm)
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{ return cond<<28 | 0xe<<24 | opcode_1<<21 | L<<20 | CRn<<16 | Rd<<12 | cp_num<<8 | opcode_2<<5 | 1<<4 | CRm; }
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inline int COREG2(int cond, int L, int Rn, int Rd, int cp_num, int opcode, int CRm)
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@ -270,14 +270,17 @@ const int N_GPRS = 16;
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const int N_FPRS = 16;
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const uint32_t GPR_MASK = 0xffff;
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const uint32_t FPR_MASK = 0xffff0000;
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// for source-to-destination masks
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const uint64_t GPR_MASK64 = GPR_MASK | (uint64_t)GPR_MASK << 32;
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// making the following const somehow breaks debug symbol output in GDB
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/* const */ uint64_t FPR_MASK64 = FPR_MASK | (uint64_t)FPR_MASK << 32;
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inline bool isFpr(Assembler::Register* reg) {
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return reg->low >= N_GPRS;
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}
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inline int toFpr(Assembler::Register* reg) {
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return reg->low - N_GPRS;
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}
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inline int fpr(Assembler::Register* reg) { return reg->low - N_GPRS; }
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inline int fpr(int reg) { return reg - N_GPRS; }
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const unsigned FrameHeaderSize = 1;
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@ -584,7 +587,7 @@ using namespace isa;
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inline void emit(Context* con, int code) { con->code.append4(code); }
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inline int newTemp(Context* con) {
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return con->client->acquireTemporary();
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return con->client->acquireTemporary(GPR_MASK);
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}
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inline int newTemp(Context* con, unsigned mask) {
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@ -920,13 +923,12 @@ moveRR(Context* con, unsigned srcSize, Assembler::Register* src,
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bool srcIsFpr = isFpr(src);
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bool dstIsFpr = isFpr(dst);
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if (srcIsFpr || dstIsFpr) { // floating-point register(s) involved
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/**/fprintf(stderr, ">>>>>>>>>>>>>>>>>>>>>>>> %d <- %d\n", dst->low, src->low);
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// FPR to FPR
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if (srcIsFpr && dstIsFpr) emit(con, fcpys(toFpr(dst), toFpr(src)));
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if (srcIsFpr && dstIsFpr) emit(con, fcpys(fpr(dst), fpr(src)));
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// FPR to GPR
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else if (srcIsFpr) emit(con, fmrs(dst->low, toFpr(src)));
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else if (srcIsFpr) emit(con, fmrs(dst->low, fpr(src)));
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// GPR to FPR
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else emit(con, fmsr(toFpr(dst), src->low));
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else emit(con, fmsr(fpr(dst), src->low));
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return;
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}
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@ -990,7 +992,6 @@ moveCR2(Context* con, unsigned size, Assembler::Constant* src,
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{
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if (isFpr(dst)) { // floating-point
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Assembler::Register tmp = makeTemp(con);
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/**/fprintf(stderr, ">>>>>>>>>>>>>>>>>>>>>>>> %d <- 0x%llx\n", tmp.low, getValue(src));
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moveCR2(con, size, src, &tmp, 0);
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moveRR(con, size, &tmp, size, dst);
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freeTemp(con, tmp);
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@ -1096,88 +1097,86 @@ void multiplyR(Context* con, unsigned size, Assembler::Register* a, Assembler::R
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void floatAbsoluteRR(Context* con, unsigned size, Assembler::Register* a, unsigned UNUSED, Assembler::Register* b) {
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if (size == 8) {
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emit(con, fabsd(b->low, a->low));
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emit(con, fabsd(fpr(b), fpr(a)));
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} else {
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emit(con, fabss(b->low, a->low));
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emit(con, fabss(fpr(b), fpr(a)));
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}
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}
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void floatNegateRR(Context* con, unsigned size, Assembler::Register* a, unsigned UNUSED, Assembler::Register* b) {
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if (size == 8) {
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/**/fprintf(stderr, ">>>>>>>>>>>>>>>>>>>>>>>> invalid 64-bit Scheiße\n");
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emit(con, fnegd(b->low, a->low));
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emit(con, fnegd(fpr(b), fpr(a)));
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} else {
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/**/fprintf(stderr, ">>>>>>>>>>>>>>>>>>>>>>>> %d <- -%d\n", b->low, a->low);
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emit(con, fnegs(b->low, a->low));
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emit(con, fnegs(fpr(b), fpr(a)));
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}
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}
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void float2FloatRR(Context* con, unsigned size, Assembler::Register* a, unsigned UNUSED, Assembler::Register* b) {
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if (size == 8) {
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emit(con, fcvtsd(b->low, a->low));
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emit(con, fcvtsd(fpr(b), fpr(a)));
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} else {
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emit(con, fcvtds(b->low, a->low));
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emit(con, fcvtds(fpr(b), fpr(a)));
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}
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}
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void float2IntRR(Context* con, unsigned size, Assembler::Register* a, unsigned UNUSED, Assembler::Register* b) {
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int tmp = newTemp(con, FPR_MASK);
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int ftmp = fpr(tmp);
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if (size == 8) { // double to int
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emit(con, ftosid(tmp, a->low));
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emit(con, ftosizd(ftmp, fpr(a)));
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} else { // float to int
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emit(con, ftosis(tmp, a->low));
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emit(con, ftosizs(ftmp, fpr(a)));
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} // else thunked
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emit(con, fmrs(b->low, tmp));
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emit(con, fmrs(b->low, ftmp));
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freeTemp(con, tmp);
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}
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void int2FloatRR(Context* con, unsigned UNUSED, Assembler::Register* a, unsigned size, Assembler::Register* b) {
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emit(con, fmsr(b->low, a->low));
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emit(con, fmsr(fpr(b), a->low));
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if (size == 8) { // int to double
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emit(con, fsitod(b->low, b->low));
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emit(con, fsitod(fpr(b), fpr(b)));
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} else { // int to float
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emit(con, fsitos(b->low, b->low));
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emit(con, fsitos(fpr(b), fpr(b)));
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} // else thunked
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}
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void floatSqrtRR(Context* con, unsigned size, Assembler::Register* a, unsigned UNUSED, Assembler::Register* b) {
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if (size == 8) {
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emit(con, fsqrtd(b->low, a->low));
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if (size == 8) {
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emit(con, fsqrtd(fpr(b), fpr(a)));
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} else {
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emit(con, fsqrts(b->low, a->low));
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emit(con, fsqrts(fpr(b), fpr(a)));
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}
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}
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void floatAddR(Context* con, unsigned size, Assembler::Register* a, Assembler::Register* b, Assembler::Register* t) {
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if (size == 8) {
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emit(con, faddd(t->low, a->low, b->low));
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if (size == 8) {
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emit(con, faddd(fpr(t), fpr(a), fpr(b)));
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} else {
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fprintf(stderr, "$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ %d <- %d + %d\n", toFpr(t), toFpr(a), toFpr(b));
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emit(con, fadds(toFpr(t), toFpr(a), toFpr(b)));
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emit(con, fadds(fpr(t), fpr(a), fpr(b)));
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}
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}
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void floatSubtractR(Context* con, unsigned size, Assembler::Register* a, Assembler::Register* b, Assembler::Register* t) {
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if (size == 8) {
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emit(con, fsubd(t->low, a->low, b->low));
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if (size == 8) {
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emit(con, fsubd(fpr(t), fpr(b), fpr(a)));
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} else {
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emit(con, fsubs(t->low, a->low, b->low));
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emit(con, fsubs(fpr(t), fpr(b), fpr(a)));
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}
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}
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void floatMultiplyR(Context* con, unsigned size, Assembler::Register* a, Assembler::Register* b, Assembler::Register* t) {
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if (size == 8) {
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emit(con, fmuld(t->low, a->low, b->low));
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emit(con, fmuld(fpr(t), fpr(a), fpr(b)));
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} else {
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emit(con, fmuls(t->low, a->low, b->low));
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emit(con, fmuls(fpr(t), fpr(a), fpr(b)));
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}
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}
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void floatDivideR(Context* con, unsigned size, Assembler::Register* a, Assembler::Register* b, Assembler::Register* t) {
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if (size == 8) {
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emit(con, fdivd(t->low, a->low, b->low));
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emit(con, fdivd(fpr(t), fpr(b), fpr(a)));
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} else {
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emit(con, fdivs(t->low, a->low, b->low));
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emit(con, fdivs(fpr(t), fpr(b), fpr(a)));
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}
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}
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@ -1242,12 +1241,11 @@ store(Context* con, unsigned size, Assembler::Register* src,
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if (isFpr(src)) { // floating-point store
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if (size == 4) {
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/**/fprintf(stderr, ">>>>>>>>>>>>>>>>>>>>>>>> fpr store base-indexed\n");
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Assembler::Register base_(base),
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normalized_(normalized),
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absAddr = makeTemp(con);
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addR(con, size, &base_, &normalized_, &absAddr);
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emit(con, fsts(toFpr(src), absAddr.low));
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emit(con, fsts(fpr(src), absAddr.low));
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freeTemp(con, absAddr);
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}
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else abort(con);
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@ -1281,8 +1279,7 @@ store(Context* con, unsigned size, Assembler::Register* src,
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or (size != 2 and abs(offset) == (abs(offset) & 0xFFF)))
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{
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if (isFpr(src)) {
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/**/fprintf(stderr, ">>>>>>>>>>>>>>>>>>>>>>>> [%d + 0x%x] <- %d\n", base, offset, src->low);
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if (size == 4) emit(con, fsts(toFpr(src), base, offset));
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if (size == 4) emit(con, fsts(fpr(src), base, offset));
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else abort(con);
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} else {
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switch (size) {
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@ -1358,12 +1355,11 @@ load(Context* con, unsigned srcSize, int base, int offset, int index,
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if (isFpr(dst)) { // floating-point store
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if (srcSize == 4) {
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/**/fprintf(stderr, ">>>>>>>>>>>>>>>>>>>>>>>> fpr load base-indexed\n");
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Assembler::Register base_(base),
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normalized_(normalized),
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absAddr = makeTemp(con);
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addR(con, srcSize, &base_, &normalized_, &absAddr);
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emit(con, flds(toFpr(dst), absAddr.low));
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emit(con, flds(fpr(dst), absAddr.low));
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freeTemp(con, absAddr);
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}
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else abort(con);
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@ -1414,8 +1410,7 @@ load(Context* con, unsigned srcSize, int base, int offset, int index,
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and abs(offset) == (abs(offset) & 0xFFF)))
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{
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if (isFpr(dst)) {
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/**/fprintf(stderr, ">>>>>>>>>>>>>>>>>>>>>>>> %d <- [%d + 0x%x]\n", dst->low, base, offset);
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if (srcSize == 4) emit(con, flds(toFpr(dst), base, offset));
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if (srcSize == 4) emit(con, flds(fpr(dst), base, offset));
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else abort(con);
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} else {
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switch (srcSize) {
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@ -1581,14 +1576,15 @@ compareRR(Context* c, unsigned aSize UNUSED, Assembler::Register* a,
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unsigned bSize UNUSED, Assembler::Register* b)
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{
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assert(c, aSize == 4 and bSize == 4);
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assert(c, b->low != a->low);
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assert(c, !(isFpr(a) ^ isFpr(b)));
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if (isFpr(a)) {
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emit(c, fcmps(toFpr(b), toFpr(a)));
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emit(c, fcmps(fpr(b), fpr(a)));
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emit(c, fmstat());
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} else {
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assert(c, b->low != a->low);
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emit(c, cmp(b->low, a->low));
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}
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else emit(c, cmp(b->low, a->low));
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}
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void
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@ -1699,6 +1695,7 @@ branchLong(Context* c, TernaryOperation op, Assembler::Operand* al,
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switch (op) {
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case JumpIfEqual:
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case JumpIfFloatEqual:
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next = c->code.length();
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emit(c, bne(0));
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@ -1707,6 +1704,7 @@ branchLong(Context* c, TernaryOperation op, Assembler::Operand* al,
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break;
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case JumpIfNotEqual:
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case JumpIfFloatNotEqual:
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conditional(c, bne(0), target);
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compareSigned(c, 4, al, 4, bl);
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@ -1714,6 +1712,7 @@ branchLong(Context* c, TernaryOperation op, Assembler::Operand* al,
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break;
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case JumpIfLess:
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case JumpIfFloatLess:
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conditional(c, blt(0), target);
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next = c->code.length();
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@ -1724,6 +1723,7 @@ branchLong(Context* c, TernaryOperation op, Assembler::Operand* al,
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break;
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case JumpIfGreater:
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case JumpIfFloatGreater:
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conditional(c, bgt(0), target);
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next = c->code.length();
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@ -1734,6 +1734,7 @@ branchLong(Context* c, TernaryOperation op, Assembler::Operand* al,
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break;
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case JumpIfLessOrEqual:
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case JumpIfFloatLessOrEqual:
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conditional(c, blt(0), target);
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next = c->code.length();
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@ -1744,6 +1745,7 @@ branchLong(Context* c, TernaryOperation op, Assembler::Operand* al,
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break;
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case JumpIfGreaterOrEqual:
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case JumpIfFloatGreaterOrEqual:
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conditional(c, bgt(0), target);
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next = c->code.length();
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@ -2326,13 +2328,16 @@ class MyArchitecture: public Assembler::Architecture {
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break;
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case Absolute:
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*thunk = true;
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break;
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case FloatAbsolute:
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case FloatSquareRoot:
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case FloatNegate:
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case Float2Float:
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if (vfpSupported()) {
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*aTypeMask = (1 << RegisterOperand);
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*aRegisterMask = FPR_MASK;
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*aRegisterMask = FPR_MASK64;
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} else {
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*thunk = true;
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}
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@ -2341,7 +2346,7 @@ class MyArchitecture: public Assembler::Architecture {
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case Float2Int:
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if (vfpSupported() && bSize == 4 && aSize == 4) {
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*aTypeMask = (1 << RegisterOperand);
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*aRegisterMask = FPR_MASK;
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*aRegisterMask = FPR_MASK64;
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} else {
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*thunk = true;
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}
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@ -2350,7 +2355,7 @@ class MyArchitecture: public Assembler::Architecture {
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case Int2Float:
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if (vfpSupported() && aSize == 4 && bSize == 4) {
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*aTypeMask = (1 << RegisterOperand);
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*aRegisterMask = FPR_MASK;
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*aRegisterMask = GPR_MASK64;
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} else {
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*thunk = true;
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}
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@ -2363,8 +2368,8 @@ class MyArchitecture: public Assembler::Architecture {
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virtual void planDestination
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(BinaryOperation op,
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unsigned, uint8_t, uint64_t,
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unsigned, uint8_t* bTypeMask, uint64_t* bRegisterMask)
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unsigned, uint8_t aTypeMask, uint64_t,
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unsigned , uint8_t* bTypeMask, uint64_t* bRegisterMask)
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{
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*bTypeMask = (1 << RegisterOperand) | (1 << MemoryOperand);
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*bRegisterMask = ~static_cast<uint64_t>(0);
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@ -2374,6 +2379,26 @@ class MyArchitecture: public Assembler::Architecture {
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*bTypeMask = (1 << RegisterOperand);
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break;
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case FloatAbsolute:
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case FloatSquareRoot:
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case FloatNegate:
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case Float2Float:
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case Int2Float:
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*bTypeMask = (1 << RegisterOperand);
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*bRegisterMask = FPR_MASK64;
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break;
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case Float2Int:
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*bTypeMask = (1 << RegisterOperand);
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*bRegisterMask = GPR_MASK64;
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break;
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case Move:
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if (!(aTypeMask & 1 << RegisterOperand)) {
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*bTypeMask = 1 << RegisterOperand;
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}
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break;
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default:
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break;
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}
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@ -2382,7 +2407,7 @@ class MyArchitecture: public Assembler::Architecture {
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virtual void planMove
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(unsigned, uint8_t* srcTypeMask, uint64_t* srcRegisterMask,
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uint8_t* tmpTypeMask, uint64_t* tmpRegisterMask,
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uint8_t dstTypeMask, uint64_t)
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uint8_t dstTypeMask, uint64_t dstRegisterMask)
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{
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*srcTypeMask = ~0;
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*srcRegisterMask = ~static_cast<uint64_t>(0);
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@ -2394,6 +2419,11 @@ class MyArchitecture: public Assembler::Architecture {
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// can't move directly from memory or constant to memory
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*srcTypeMask = 1 << RegisterOperand;
|
||||
*tmpTypeMask = 1 << RegisterOperand;
|
||||
*tmpRegisterMask = GPR_MASK64;
|
||||
} else if (dstTypeMask & 1 << RegisterOperand &&
|
||||
dstRegisterMask & FPR_MASK) {
|
||||
*srcTypeMask = *tmpTypeMask = 1 << RegisterOperand |
|
||||
1 << MemoryOperand;
|
||||
*tmpRegisterMask = ~static_cast<uint64_t>(0);
|
||||
}
|
||||
}
|
||||
@ -2429,6 +2459,7 @@ class MyArchitecture: public Assembler::Architecture {
|
||||
|
||||
case Divide:
|
||||
case Remainder:
|
||||
case FloatRemainder:
|
||||
*thunk = true;
|
||||
break;
|
||||
|
||||
@ -2436,7 +2467,14 @@ class MyArchitecture: public Assembler::Architecture {
|
||||
case FloatSubtract:
|
||||
case FloatMultiply:
|
||||
case FloatDivide:
|
||||
case FloatRemainder:
|
||||
if (vfpSupported()) {
|
||||
*aTypeMask = *bTypeMask = (1 << RegisterOperand);
|
||||
*aRegisterMask = *bRegisterMask = FPR_MASK64;
|
||||
} else {
|
||||
*thunk = true;
|
||||
}
|
||||
break;
|
||||
|
||||
case JumpIfFloatEqual:
|
||||
case JumpIfFloatNotEqual:
|
||||
case JumpIfFloatLess:
|
||||
@ -2449,7 +2487,7 @@ class MyArchitecture: public Assembler::Architecture {
|
||||
case JumpIfFloatGreaterOrEqualOrUnordered:
|
||||
if (vfpSupported()) {
|
||||
*aTypeMask = *bTypeMask = (1 << RegisterOperand);
|
||||
*aRegisterMask = *bRegisterMask = FPR_MASK;
|
||||
*aRegisterMask = *bRegisterMask = FPR_MASK64;
|
||||
} else {
|
||||
*thunk = true;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user