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https://github.com/corda/corda.git
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begin converting to setLowHighRegisterMasks
This commit is contained in:
Joshua Warner
parent
ac72aa8b91
commit
1110d3ff50
@ -56,6 +56,11 @@ class OperandMask {
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OperandMask() : typeMask(~0), lowRegisterMask(~static_cast<uint64_t>(0)), highRegisterMask(~static_cast<uint64_t>(0))
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{
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}
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void setLowHighRegisterMasks(uint64_t lowRegisterMask, uint64_t highRegisterMask) {
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this->lowRegisterMask = lowRegisterMask | (highRegisterMask << 32);
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this->highRegisterMask = highRegisterMask;
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}
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};
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class Architecture {
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@ -53,7 +53,7 @@ class SiteMask {
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static SiteMask highPart(const OperandMask& mask)
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{
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return SiteMask(mask.typeMask, mask.lowRegisterMask >> 32, AnyFrameIndex);
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return SiteMask(mask.typeMask, mask.highRegisterMask, AnyFrameIndex);
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}
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uint8_t typeMask;
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@ -402,7 +402,7 @@ class MyArchitecture : public Architecture {
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bool* thunk)
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{
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aMask.typeMask = (1 << lir::RegisterOperand) | (1 << lir::ConstantOperand);
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aMask.lowRegisterMask = ~static_cast<uint64_t>(0);
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aMask.setLowHighRegisterMasks(~static_cast<uint64_t>(0), ~static_cast<uint64_t>(0));
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*thunk = false;
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}
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@ -414,12 +414,12 @@ class MyArchitecture : public Architecture {
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{
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*thunk = false;
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aMask.typeMask = ~0;
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aMask.lowRegisterMask = GPR_MASK64;
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aMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
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switch (op) {
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case lir::Negate:
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aMask.typeMask = (1 << lir::RegisterOperand);
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aMask.lowRegisterMask = GPR_MASK64;
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aMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
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break;
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case lir::Absolute:
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@ -432,7 +432,7 @@ class MyArchitecture : public Architecture {
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case lir::Float2Float:
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if (vfpSupported()) {
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aMask.typeMask = (1 << lir::RegisterOperand);
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aMask.lowRegisterMask = FPR_MASK64;
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aMask.setLowHighRegisterMasks(FPR_MASK, FPR_MASK);
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} else {
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*thunk = true;
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}
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@ -445,7 +445,7 @@ class MyArchitecture : public Architecture {
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// cases properly.
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if (false && vfpSupported() && bSize == 4) {
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aMask.typeMask = (1 << lir::RegisterOperand);
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aMask.lowRegisterMask = FPR_MASK64;
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aMask.setLowHighRegisterMasks(FPR_MASK, FPR_MASK);
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} else {
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*thunk = true;
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}
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@ -454,7 +454,7 @@ class MyArchitecture : public Architecture {
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case lir::Int2Float:
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if (vfpSupported() && aSize == 4) {
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aMask.typeMask = (1 << lir::RegisterOperand);
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aMask.lowRegisterMask = GPR_MASK64;
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aMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
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} else {
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*thunk = true;
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}
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@ -472,12 +472,12 @@ class MyArchitecture : public Architecture {
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OperandMask& bMask)
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{
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bMask.typeMask = (1 << lir::RegisterOperand) | (1 << lir::MemoryOperand);
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bMask.lowRegisterMask = GPR_MASK64;
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bMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
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switch (op) {
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case lir::Negate:
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bMask.typeMask = (1 << lir::RegisterOperand);
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bMask.lowRegisterMask = GPR_MASK64;
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bMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
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break;
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case lir::FloatAbsolute:
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@ -486,12 +486,12 @@ class MyArchitecture : public Architecture {
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case lir::Float2Float:
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case lir::Int2Float:
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bMask.typeMask = (1 << lir::RegisterOperand);
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bMask.lowRegisterMask = FPR_MASK64;
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bMask.setLowHighRegisterMasks(FPR_MASK, FPR_MASK);
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break;
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case lir::Float2Int:
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bMask.typeMask = (1 << lir::RegisterOperand);
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bMask.lowRegisterMask = GPR_MASK64;
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bMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
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break;
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case lir::Move:
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@ -511,21 +511,21 @@ class MyArchitecture : public Architecture {
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const OperandMask& dstMask)
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{
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srcMask.typeMask = ~0;
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srcMask.lowRegisterMask = ~static_cast<uint64_t>(0);
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srcMask.setLowHighRegisterMasks(~static_cast<uint64_t>(0), ~static_cast<uint64_t>(0));
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tmpMask.typeMask = 0;
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tmpMask.lowRegisterMask = 0;
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tmpMask.setLowHighRegisterMasks(0, 0);
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if (dstMask.typeMask & (1 << lir::MemoryOperand)) {
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// can't move directly from memory or constant to memory
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srcMask.typeMask = 1 << lir::RegisterOperand;
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tmpMask.typeMask = 1 << lir::RegisterOperand;
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tmpMask.lowRegisterMask = GPR_MASK64;
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tmpMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
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} else if (vfpSupported() && dstMask.typeMask & 1 << lir::RegisterOperand
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&& dstMask.lowRegisterMask & FPR_MASK) {
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srcMask.typeMask = tmpMask.typeMask = 1 << lir::RegisterOperand
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| 1 << lir::MemoryOperand;
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tmpMask.lowRegisterMask = ~static_cast<uint64_t>(0);
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tmpMask.setLowHighRegisterMasks(~static_cast<uint64_t>(0), ~static_cast<uint64_t>(0));
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}
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}
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@ -538,10 +538,10 @@ class MyArchitecture : public Architecture {
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bool* thunk)
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{
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aMask.typeMask = (1 << lir::RegisterOperand) | (1 << lir::ConstantOperand);
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aMask.lowRegisterMask = GPR_MASK64;
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aMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
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bMask.typeMask = (1 << lir::RegisterOperand);
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bMask.lowRegisterMask = GPR_MASK64;
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bMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
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*thunk = false;
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@ -572,8 +572,9 @@ class MyArchitecture : public Architecture {
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case lir::FloatMultiply:
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case lir::FloatDivide:
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if (vfpSupported()) {
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aMask.typeMask = bMask.typeMask = (1 << lir::RegisterOperand);
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aMask.lowRegisterMask = bMask.lowRegisterMask = FPR_MASK64;
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bMask.typeMask = (1 << lir::RegisterOperand);
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aMask.setLowHighRegisterMasks(FPR_MASK, FPR_MASK);
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bMask = aMask;
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} else {
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*thunk = true;
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}
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@ -590,8 +591,9 @@ class MyArchitecture : public Architecture {
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case lir::JumpIfFloatLessOrEqualOrUnordered:
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case lir::JumpIfFloatGreaterOrEqualOrUnordered:
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if (vfpSupported()) {
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aMask.typeMask = bMask.typeMask = (1 << lir::RegisterOperand);
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aMask.lowRegisterMask = bMask.lowRegisterMask = FPR_MASK64;
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aMask.typeMask = (1 << lir::RegisterOperand);
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aMask.setLowHighRegisterMasks(FPR_MASK, FPR_MASK);
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bMask = aMask;
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} else {
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*thunk = true;
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}
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@ -612,10 +614,11 @@ class MyArchitecture : public Architecture {
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{
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if (isBranch(op)) {
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cMask.typeMask = (1 << lir::ConstantOperand);
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cMask.lowRegisterMask = 0;
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cMask.setLowHighRegisterMasks(0, 0);
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} else {
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cMask.typeMask = (1 << lir::RegisterOperand);
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cMask.lowRegisterMask = bMask.lowRegisterMask;
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cMask.highRegisterMask = bMask.highRegisterMask;
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}
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}
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@ -512,22 +512,20 @@ class MyArchitecture : public Architecture {
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unsigned bSize,
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bool* thunk)
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{
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aMask.lowRegisterMask = GeneralRegisterMask
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| (static_cast<uint64_t>(GeneralRegisterMask) << 32);
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aMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
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*thunk = false;
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switch (op) {
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case lir::Negate:
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aMask.typeMask = (1 << lir::RegisterOperand);
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aMask.lowRegisterMask = (static_cast<uint64_t>(1) << (rdx + 32))
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| (static_cast<uint64_t>(1) << rax);
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aMask.setLowHighRegisterMasks(1 << rax, 1 << rdx);
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break;
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case lir::Absolute:
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if (aSize <= TargetBytesPerWord) {
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aMask.typeMask = (1 << lir::RegisterOperand);
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aMask.lowRegisterMask = (static_cast<uint64_t>(1) << rax);
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aMask.setLowHighRegisterMasks(1 << rax, 0);
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} else {
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*thunk = true;
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}
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@ -536,8 +534,7 @@ class MyArchitecture : public Architecture {
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case lir::FloatAbsolute:
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if (useSSE(&c)) {
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aMask.typeMask = (1 << lir::RegisterOperand);
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aMask.lowRegisterMask = (static_cast<uint64_t>(FloatRegisterMask) << 32)
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| FloatRegisterMask;
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aMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
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} else {
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*thunk = true;
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}
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@ -547,7 +544,7 @@ class MyArchitecture : public Architecture {
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// floatNegateRR does not support doubles
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if (useSSE(&c) and aSize == 4 and bSize == 4) {
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aMask.typeMask = (1 << lir::RegisterOperand);
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aMask.lowRegisterMask = FloatRegisterMask;
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aMask.setLowHighRegisterMasks(FloatRegisterMask, 0);
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} else {
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*thunk = true;
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}
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@ -557,8 +554,7 @@ class MyArchitecture : public Architecture {
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if (useSSE(&c)) {
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aMask.typeMask = (1 << lir::RegisterOperand)
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| (1 << lir::MemoryOperand);
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aMask.lowRegisterMask = (static_cast<uint64_t>(FloatRegisterMask) << 32)
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| FloatRegisterMask;
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aMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
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} else {
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*thunk = true;
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}
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@ -568,8 +564,7 @@ class MyArchitecture : public Architecture {
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if (useSSE(&c)) {
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aMask.typeMask = (1 << lir::RegisterOperand)
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| (1 << lir::MemoryOperand);
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aMask.lowRegisterMask = (static_cast<uint64_t>(FloatRegisterMask) << 32)
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| FloatRegisterMask;
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aMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
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} else {
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*thunk = true;
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}
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@ -583,8 +578,7 @@ class MyArchitecture : public Architecture {
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if (false and useSSE(&c) and bSize <= TargetBytesPerWord) {
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aMask.typeMask = (1 << lir::RegisterOperand)
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| (1 << lir::MemoryOperand);
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aMask.lowRegisterMask = (static_cast<uint64_t>(FloatRegisterMask) << 32)
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| FloatRegisterMask;
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aMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
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} else {
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*thunk = true;
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}
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@ -594,9 +588,7 @@ class MyArchitecture : public Architecture {
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if (useSSE(&c) and aSize <= TargetBytesPerWord) {
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aMask.typeMask = (1 << lir::RegisterOperand)
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| (1 << lir::MemoryOperand);
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aMask.lowRegisterMask
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= GeneralRegisterMask
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| (static_cast<uint64_t>(GeneralRegisterMask) << 32);
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aMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
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} else {
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*thunk = true;
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}
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@ -604,7 +596,7 @@ class MyArchitecture : public Architecture {
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case lir::Move:
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aMask.typeMask = ~0;
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aMask.lowRegisterMask = ~static_cast<uint64_t>(0);
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aMask.setLowHighRegisterMasks(~static_cast<uint64_t>(0), ~static_cast<uint64_t>(0));
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if (TargetBytesPerWord == 4) {
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if (aSize == 4 and bSize == 8) {
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@ -612,13 +604,13 @@ class MyArchitecture : public Architecture {
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| (1 << lir::MemoryOperand);
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const uint32_t mask = GeneralRegisterMask
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& ~((1 << rax) | (1 << rdx));
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aMask.lowRegisterMask = (static_cast<uint64_t>(mask) << 32) | mask;
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aMask.setLowHighRegisterMasks(mask, mask);
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} else if (aSize == 1 or bSize == 1) {
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aMask.typeMask = (1 << lir::RegisterOperand)
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| (1 << lir::MemoryOperand);
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const uint32_t mask = (1 << rax) | (1 << rcx) | (1 << rdx)
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| (1 << rbx);
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aMask.lowRegisterMask = (static_cast<uint64_t>(mask) << 32) | mask;
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aMask.setLowHighRegisterMasks(mask, mask);
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}
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}
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break;
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@ -635,23 +627,24 @@ class MyArchitecture : public Architecture {
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OperandMask& bMask)
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{
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bMask.typeMask = ~0;
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bMask.lowRegisterMask = GeneralRegisterMask
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| (static_cast<uint64_t>(GeneralRegisterMask) << 32);
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bMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
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switch (op) {
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case lir::Absolute:
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bMask.typeMask = (1 << lir::RegisterOperand);
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bMask.lowRegisterMask = (static_cast<uint64_t>(1) << rax);
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bMask.setLowHighRegisterMasks(1 << rax, 0);
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break;
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case lir::FloatAbsolute:
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bMask.typeMask = (1 << lir::RegisterOperand);
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bMask.lowRegisterMask = aMask.lowRegisterMask;
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bMask.highRegisterMask = aMask.highRegisterMask;
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break;
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case lir::Negate:
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bMask.typeMask = (1 << lir::RegisterOperand);
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bMask.lowRegisterMask = aMask.lowRegisterMask;
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bMask.highRegisterMask = aMask.highRegisterMask;
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break;
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case lir::FloatNegate:
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@ -659,8 +652,7 @@ class MyArchitecture : public Architecture {
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case lir::Float2Float:
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case lir::Int2Float:
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bMask.typeMask = (1 << lir::RegisterOperand);
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bMask.lowRegisterMask = (static_cast<uint64_t>(FloatRegisterMask) << 32)
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| FloatRegisterMask;
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bMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
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break;
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case lir::Float2Int:
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@ -671,18 +663,14 @@ class MyArchitecture : public Architecture {
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if (aMask.typeMask
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& ((1 << lir::MemoryOperand) | 1 << lir::AddressOperand)) {
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bMask.typeMask = (1 << lir::RegisterOperand);
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bMask.lowRegisterMask = GeneralRegisterMask
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| (static_cast<uint64_t>(GeneralRegisterMask)
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<< 32) | FloatRegisterMask;
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bMask.setLowHighRegisterMasks(GeneralRegisterMask | FloatRegisterMask, GeneralRegisterMask);
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} else if (aMask.typeMask & (1 << lir::RegisterOperand)) {
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bMask.typeMask = (1 << lir::RegisterOperand)
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| (1 << lir::MemoryOperand);
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if (aMask.lowRegisterMask & FloatRegisterMask) {
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bMask.lowRegisterMask = FloatRegisterMask;
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bMask.setLowHighRegisterMasks(FloatRegisterMask, 0);
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} else {
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bMask.lowRegisterMask
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= GeneralRegisterMask
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| (static_cast<uint64_t>(GeneralRegisterMask) << 32);
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bMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
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}
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} else {
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bMask.typeMask = (1 << lir::RegisterOperand)
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@ -691,12 +679,11 @@ class MyArchitecture : public Architecture {
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if (TargetBytesPerWord == 4) {
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if (aSize == 4 and bSize == 8) {
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bMask.lowRegisterMask = (static_cast<uint64_t>(1) << (rdx + 32))
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| (static_cast<uint64_t>(1) << rax);
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bMask.setLowHighRegisterMasks(1 << rax, 1 << rdx);
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} else if (aSize == 1 or bSize == 1) {
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const uint32_t mask = (1 << rax) | (1 << rcx) | (1 << rdx)
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| (1 << rbx);
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bMask.lowRegisterMask = (static_cast<uint64_t>(mask) << 32) | mask;
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bMask.setLowHighRegisterMasks(mask, mask);
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}
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}
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break;
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@ -712,32 +699,26 @@ class MyArchitecture : public Architecture {
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const OperandMask& dstMask)
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{
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srcMask.typeMask = ~0;
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srcMask.lowRegisterMask = ~static_cast<uint64_t>(0);
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srcMask.setLowHighRegisterMasks(~static_cast<uint64_t>(0), ~static_cast<uint64_t>(0));
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tmpMask.typeMask = 0;
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tmpMask.lowRegisterMask = 0;
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tmpMask.setLowHighRegisterMasks(0, 0);
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if (dstMask.typeMask & (1 << lir::MemoryOperand)) {
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// can't move directly from memory to memory
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srcMask.typeMask = (1 << lir::RegisterOperand)
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| (1 << lir::ConstantOperand);
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tmpMask.typeMask = 1 << lir::RegisterOperand;
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tmpMask.lowRegisterMask
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= GeneralRegisterMask
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| (static_cast<uint64_t>(GeneralRegisterMask) << 32);
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tmpMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
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} else if (dstMask.typeMask & (1 << lir::RegisterOperand)) {
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if (size > TargetBytesPerWord) {
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// can't move directly from FPR to GPR or vice-versa for
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// values larger than the GPR size
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if (dstMask.lowRegisterMask & FloatRegisterMask) {
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srcMask.lowRegisterMask
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= FloatRegisterMask
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| (static_cast<uint64_t>(FloatRegisterMask) << 32);
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srcMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
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tmpMask.typeMask = 1 << lir::MemoryOperand;
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} else if (dstMask.lowRegisterMask & GeneralRegisterMask) {
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srcMask.lowRegisterMask
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= GeneralRegisterMask
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| (static_cast<uint64_t>(GeneralRegisterMask) << 32);
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srcMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
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tmpMask.typeMask = 1 << lir::MemoryOperand;
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}
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}
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@ -749,9 +730,7 @@ class MyArchitecture : public Architecture {
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} else {
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tmpMask.typeMask = (1 << lir::RegisterOperand)
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| (1 << lir::MemoryOperand);
|
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tmpMask.lowRegisterMask
|
||||
= GeneralRegisterMask
|
||||
| (static_cast<uint64_t>(GeneralRegisterMask) << 32);
|
||||
tmpMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -766,12 +745,10 @@ class MyArchitecture : public Architecture {
|
||||
bool* thunk)
|
||||
{
|
||||
aMask.typeMask = (1 << lir::RegisterOperand) | (1 << lir::ConstantOperand);
|
||||
aMask.lowRegisterMask = GeneralRegisterMask
|
||||
| (static_cast<uint64_t>(GeneralRegisterMask) << 32);
|
||||
aMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
|
||||
|
||||
bMask.typeMask = (1 << lir::RegisterOperand);
|
||||
bMask.lowRegisterMask = GeneralRegisterMask
|
||||
| (static_cast<uint64_t>(GeneralRegisterMask) << 32);
|
||||
bMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
|
||||
|
||||
*thunk = false;
|
||||
|
||||
@ -785,10 +762,8 @@ class MyArchitecture : public Architecture {
|
||||
| (1 << lir::MemoryOperand);
|
||||
bMask.typeMask = (1 << lir::RegisterOperand);
|
||||
|
||||
const uint64_t mask = (static_cast<uint64_t>(FloatRegisterMask) << 32)
|
||||
| FloatRegisterMask;
|
||||
aMask.lowRegisterMask = mask;
|
||||
bMask.lowRegisterMask = mask;
|
||||
aMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
|
||||
bMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
|
||||
} else {
|
||||
*thunk = true;
|
||||
}
|
||||
@ -801,11 +776,11 @@ class MyArchitecture : public Architecture {
|
||||
case lir::Multiply:
|
||||
if (TargetBytesPerWord == 4 and aSize == 8) {
|
||||
const uint32_t mask = GeneralRegisterMask & ~((1 << rax) | (1 << rdx));
|
||||
aMask.lowRegisterMask = (static_cast<uint64_t>(mask) << 32) | mask;
|
||||
bMask.lowRegisterMask = (static_cast<uint64_t>(1) << (rdx + 32)) | mask;
|
||||
aMask.setLowHighRegisterMasks(mask, mask);
|
||||
bMask.setLowHighRegisterMasks(mask, 1 << rdx);
|
||||
} else {
|
||||
aMask.lowRegisterMask = GeneralRegisterMask;
|
||||
bMask.lowRegisterMask = GeneralRegisterMask;
|
||||
aMask.setLowHighRegisterMasks(GeneralRegisterMask, 0);
|
||||
bMask.setLowHighRegisterMasks(GeneralRegisterMask, 0);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -814,8 +789,8 @@ class MyArchitecture : public Architecture {
|
||||
*thunk = true;
|
||||
} else {
|
||||
aMask.typeMask = (1 << lir::RegisterOperand);
|
||||
aMask.lowRegisterMask = GeneralRegisterMask & ~((1 << rax) | (1 << rdx));
|
||||
bMask.lowRegisterMask = 1 << rax;
|
||||
aMask.setLowHighRegisterMasks(GeneralRegisterMask & ~((1 << rax) | (1 << rdx)), 0);
|
||||
bMask.setLowHighRegisterMasks(1 << rax, 0);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -824,8 +799,8 @@ class MyArchitecture : public Architecture {
|
||||
*thunk = true;
|
||||
} else {
|
||||
aMask.typeMask = (1 << lir::RegisterOperand);
|
||||
aMask.lowRegisterMask = GeneralRegisterMask & ~((1 << rax) | (1 << rdx));
|
||||
bMask.lowRegisterMask = 1 << rax;
|
||||
aMask.setLowHighRegisterMasks(GeneralRegisterMask & ~((1 << rax) | (1 << rdx)), 0);
|
||||
bMask.setLowHighRegisterMasks(1 << rax, 0);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -834,13 +809,12 @@ class MyArchitecture : public Architecture {
|
||||
case lir::UnsignedShiftRight: {
|
||||
if (TargetBytesPerWord == 4 and bSize == 8) {
|
||||
const uint32_t mask = GeneralRegisterMask & ~(1 << rcx);
|
||||
aMask.lowRegisterMask = (static_cast<uint64_t>(mask) << 32) | mask;
|
||||
bMask.lowRegisterMask = (static_cast<uint64_t>(mask) << 32) | mask;
|
||||
aMask.setLowHighRegisterMasks(mask, mask);
|
||||
bMask.setLowHighRegisterMasks(mask, mask);
|
||||
} else {
|
||||
aMask.lowRegisterMask = (static_cast<uint64_t>(GeneralRegisterMask) << 32)
|
||||
| (static_cast<uint64_t>(1) << rcx);
|
||||
aMask.setLowHighRegisterMasks(static_cast<uint64_t>(1) << rcx, GeneralRegisterMask);
|
||||
const uint32_t mask = GeneralRegisterMask & ~(1 << rcx);
|
||||
bMask.lowRegisterMask = (static_cast<uint64_t>(mask) << 32) | mask;
|
||||
bMask.setLowHighRegisterMasks(mask, mask);
|
||||
}
|
||||
} break;
|
||||
|
||||
@ -856,10 +830,10 @@ class MyArchitecture : public Architecture {
|
||||
case lir::JumpIfFloatGreaterOrEqualOrUnordered:
|
||||
if (useSSE(&c)) {
|
||||
aMask.typeMask = (1 << lir::RegisterOperand);
|
||||
aMask.lowRegisterMask = (static_cast<uint64_t>(FloatRegisterMask) << 32)
|
||||
| FloatRegisterMask;
|
||||
aMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
|
||||
bMask.typeMask = aMask.typeMask;
|
||||
bMask.lowRegisterMask = aMask.lowRegisterMask;
|
||||
bMask.highRegisterMask = aMask.highRegisterMask;
|
||||
} else {
|
||||
*thunk = true;
|
||||
}
|
||||
@ -880,10 +854,11 @@ class MyArchitecture : public Architecture {
|
||||
{
|
||||
if (isBranch(op)) {
|
||||
cMask.typeMask = (1 << lir::ConstantOperand);
|
||||
cMask.lowRegisterMask = 0;
|
||||
cMask.setLowHighRegisterMasks(0, 0);
|
||||
} else {
|
||||
cMask.typeMask = (1 << lir::RegisterOperand);
|
||||
cMask.lowRegisterMask = bMask.lowRegisterMask;
|
||||
cMask.highRegisterMask = bMask.highRegisterMask;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user