add convenience (1 << lir::Operand::Type::*) shortcuts (lir::Operand::*Mask)

include/avian/codegen/lir.h

@@ -129,6 +129,11 @@ public:
   };
 
   const static unsigned TypeCount = (unsigned)Type::Memory + 1;
+
+  const static unsigned ConstantMask = 1 << (unsigned)Type::Constant;
+  const static unsigned AddressMask = 1 << (unsigned)Type::Address;
+  const static unsigned RegisterPairMask = 1 << (unsigned)Type::RegisterPair;
+  const static unsigned MemoryMask = 1 << (unsigned)Type::Memory;
 };
 
 class Constant : public Operand {

src/codegen/compiler.cpp

@@ -514,14 +514,14 @@ void steal(Context* c, Resource* r, Value* thief)
 
 SiteMask generalRegisterMask(Context* c)
 {
-  return SiteMask(1 << (unsigned)lir::Operand::Type::RegisterPair,
+  return SiteMask(lir::Operand::RegisterPairMask,
                   c->regFile->generalRegisters,
                   NoFrameIndex);
 }
 
 SiteMask generalRegisterOrConstantMask(Context* c)
 {
-  return SiteMask((1 << (unsigned)lir::Operand::Type::RegisterPair) | (1 << (unsigned)lir::Operand::Type::Constant),
+  return SiteMask(lir::Operand::RegisterPairMask | lir::Operand::ConstantMask,
                   c->regFile->generalRegisters,
                   NoFrameIndex);
 }
@@ -620,7 +620,7 @@ bool acceptForResolve(Context* c, Site* s, Read* read, const SiteMask& mask)
       return c->availableGeneralRegisterCount > ResolveRegisterReserveCount;
     } else {
       assertT(c,
-              s->match(c, SiteMask(1 << (unsigned)lir::Operand::Type::Memory, 0, AnyFrameIndex)));
+              s->match(c, SiteMask(lir::Operand::MemoryMask, 0, AnyFrameIndex)));
 
       return isHome(read->value,
                     offsetToFrameIndex(c, static_cast<MemorySite*>(s)->offset));
@@ -782,7 +782,7 @@ void saveLocals(Context* c, Event* e)
       e->addRead(
           c,
           local->value,
-          SiteMask(1 << (unsigned)lir::Operand::Type::Memory, 0, compiler::frameIndex(c, li)));
+          SiteMask(lir::Operand::MemoryMask, 0, compiler::frameIndex(c, li)));
     }
   }
 }
@@ -878,7 +878,7 @@ void maybeMove(Context* c,
       }
 
       assertT(c, thunk == 0);
-      assertT(c, dstMask.typeMask & src.typeMask & (1 << (unsigned)lir::Operand::Type::RegisterPair));
+      assertT(c, dstMask.typeMask & src.typeMask & lir::Operand::RegisterPairMask);
 
       Site* tmpTarget
           = freeRegisterSite(c, dstMask.registerMask & src.lowRegisterMask);
@@ -1635,7 +1635,7 @@ bool resolveSourceSites(Context* c,
     Read* r = live(c, v);
 
     if (r and sites[el.localIndex] == 0) {
-      SiteMask mask((1 << (unsigned)lir::Operand::Type::RegisterPair) | (1 << (unsigned)lir::Operand::Type::Memory),
+      SiteMask mask(lir::Operand::RegisterPairMask | lir::Operand::MemoryMask,
                     c->regFile->generalRegisters,
                     AnyFrameIndex);
 
@@ -1677,7 +1677,7 @@ void resolveTargetSites(Context* c,
     Read* r = live(c, v);
 
     if (r and sites[el.localIndex] == 0) {
-      SiteMask mask((1 << (unsigned)lir::Operand::Type::RegisterPair) | (1 << (unsigned)lir::Operand::Type::Memory),
+      SiteMask mask(lir::Operand::RegisterPairMask | lir::Operand::MemoryMask,
                     c->regFile->generalRegisters,
                     AnyFrameIndex);
 

src/codegen/compiler/event.cpp

@@ -415,7 +415,7 @@ class CallEvent : public Event {
             fprintf(stderr, "stack %d arg read %p\n", frameIndex, v);
           }
 
-          targetMask = SiteMask(1 << (unsigned)lir::Operand::Type::Memory, 0, frameIndex);
+          targetMask = SiteMask(lir::Operand::MemoryMask, 0, frameIndex);
         }
 
         this->addRead(c, v, targetMask);
@@ -512,7 +512,7 @@ class CallEvent : public Event {
             this->addRead(c, v, generalRegisterMask(c));
           } else {
             this->addRead(
-                c, v, SiteMask(1 << (unsigned)lir::Operand::Type::Memory, 0, frameIndex));
+                c, v, SiteMask(lir::Operand::MemoryMask, 0, frameIndex));
           }
         }
       }
@@ -544,7 +544,7 @@ class CallEvent : public Event {
 
           this->addRead(c,
                         stack->value,
-                        SiteMask(1 << (unsigned)lir::Operand::Type::Memory, 0, logicalIndex));
+                        SiteMask(lir::Operand::MemoryMask, 0, logicalIndex));
         }
 
         stack = stack->next;
@@ -866,7 +866,7 @@ class MoveEvent : public Event {
       assertT(c, srcSelectSize == c->targetInfo.pointerSize);
 
       if (dstValue->nextWord->target or live(c, dstValue->nextWord)) {
-        assertT(c, dstLowMask.typeMask & (1 << (unsigned)lir::Operand::Type::RegisterPair));
+        assertT(c, dstLowMask.typeMask & lir::Operand::RegisterPairMask);
 
         Site* low = freeRegisterSite(c, dstLowMask.registerMask);
 
@@ -897,7 +897,7 @@ class MoveEvent : public Event {
 
         srcValue->source->thaw(c, srcValue);
 
-        assertT(c, dstHighMask.typeMask & (1 << (unsigned)lir::Operand::Type::RegisterPair));
+        assertT(c, dstHighMask.typeMask & lir::Operand::RegisterPairMask);
 
         Site* high = freeRegisterSite(c, dstHighMask.registerMask);
 
@@ -1461,7 +1461,7 @@ ConstantSite* findConstantSite(Context* c, Value* v)
 void moveIfConflict(Context* c, Value* v, MemorySite* s)
 {
   if (v->reads) {
-    SiteMask mask(1 << (unsigned)lir::Operand::Type::RegisterPair, ~0, AnyFrameIndex);
+    SiteMask mask(lir::Operand::RegisterPairMask, ~0, AnyFrameIndex);
     v->reads->intersect(&mask);
     if (s->conflicts(mask)) {
       maybeMove(c, v->reads, true, false);
@@ -1873,12 +1873,12 @@ void clean(Context* c, Value* v, unsigned popIndex)
 {
   for (SiteIterator it(c, v); it.hasMore();) {
     Site* s = it.next();
-    if (not(s->match(c, SiteMask(1 << (unsigned)lir::Operand::Type::Memory, 0, AnyFrameIndex))
+    if (not(s->match(c, SiteMask(lir::Operand::MemoryMask, 0, AnyFrameIndex))
             and offsetToFrameIndex(c, static_cast<MemorySite*>(s)->offset)
                 >= popIndex)) {
       if (false
           and s->match(c,
-                       SiteMask(1 << (unsigned)lir::Operand::Type::Memory, 0, AnyFrameIndex))) {
+                       SiteMask(lir::Operand::MemoryMask, 0, AnyFrameIndex))) {
         char buffer[256];
         s->toString(c, buffer, 256);
         fprintf(stderr,

src/codegen/compiler/read.cpp

@@ -205,7 +205,7 @@ Read* StubRead::next(Context*)
 SingleRead* read(Context* c, const SiteMask& mask, Value* successor)
 {
   assertT(c,
-          (mask.typeMask != 1 << (unsigned)lir::Operand::Type::Memory) or mask.frameIndex >= 0);
+          (mask.typeMask != lir::Operand::MemoryMask) or mask.frameIndex >= 0);
 
   return new (c->zone) SingleRead(mask, successor);
 }

src/codegen/compiler/regalloc.cpp

@@ -71,7 +71,7 @@ bool pickRegisterTarget(Context* c,
               c,
               v,
               r,
-              SiteMask(1 << (unsigned)lir::Operand::Type::RegisterPair, RegisterMask(i), NoFrameIndex),
+              SiteMask(lir::Operand::RegisterPairMask, RegisterMask(i), NoFrameIndex),
               costCalculator) + Target::MinimumRegisterCost;
 
     if (mask.containsExactly(i)) {
@@ -135,7 +135,7 @@ unsigned frameCost(Context* c,
   return resourceCost(c,
                       v,
                       c->frameResources + frameIndex,
-                      SiteMask(1 << (unsigned)lir::Operand::Type::Memory, 0, frameIndex),
+                      SiteMask(lir::Operand::MemoryMask, 0, frameIndex),
                       costCalculator) + Target::MinimumFrameCost;
 }
 
@@ -186,7 +186,7 @@ Target pickTarget(Context* c,
                   Target best,
                   CostCalculator* costCalculator)
 {
-  if (mask.typeMask & (1 << (unsigned)lir::Operand::Type::RegisterPair)) {
+  if (mask.typeMask & lir::Operand::RegisterPairMask) {
     Target mine
         = pickRegisterTarget(c, value, mask.registerMask, costCalculator);
 
@@ -198,7 +198,7 @@ Target pickTarget(Context* c,
     }
   }
 
-  if (mask.typeMask & (1 << (unsigned)lir::Operand::Type::Memory)) {
+  if (mask.typeMask & lir::Operand::MemoryMask) {
     if (mask.frameIndex >= 0) {
       Target mine(mask.frameIndex,
                   lir::Operand::Type::Memory,

src/codegen/compiler/site.cpp

@@ -152,7 +152,7 @@ class AddressSite : public Site {
 
   virtual bool match(Context*, const SiteMask& mask)
   {
-    return mask.typeMask & (1 << (unsigned)lir::Operand::Type::Address);
+    return mask.typeMask & lir::Operand::AddressMask;
   }
 
   virtual bool loneMatch(Context*, const SiteMask&)
@@ -201,7 +201,7 @@ class AddressSite : public Site {
 
   virtual SiteMask mask(Context*)
   {
-    return SiteMask(1 << (unsigned)lir::Operand::Type::Address, 0, NoFrameIndex);
+    return SiteMask(lir::Operand::AddressMask, 0, NoFrameIndex);
   }
 
   virtual SiteMask nextWordMask(Context* c, unsigned)
@@ -249,7 +249,7 @@ bool RegisterSite::match(Context* c UNUSED, const SiteMask& mask)
 {
   assertT(c, number != NoRegister);
 
-  if ((mask.typeMask & (1 << (unsigned)lir::Operand::Type::RegisterPair))) {
+  if ((mask.typeMask & lir::Operand::RegisterPairMask)) {
     return mask.registerMask.contains(number);
   } else {
     return false;
@@ -260,7 +260,7 @@ bool RegisterSite::loneMatch(Context* c UNUSED, const SiteMask& mask)
 {
   assertT(c, number != NoRegister);
 
-  if ((mask.typeMask & (1 << (unsigned)lir::Operand::Type::RegisterPair))) {
+  if ((mask.typeMask & lir::Operand::RegisterPairMask)) {
     return mask.registerMask.containsExactly(number);
   } else {
     return false;
@@ -385,7 +385,7 @@ Site* RegisterSite::makeNextWord(Context* c, unsigned)
 
 SiteMask RegisterSite::mask(Context* c UNUSED)
 {
-  return SiteMask(1 << (unsigned)lir::Operand::Type::RegisterPair, mask_, NoFrameIndex);
+  return SiteMask(lir::Operand::RegisterPairMask, mask_, NoFrameIndex);
 }
 
 SiteMask RegisterSite::nextWordMask(Context* c, unsigned)
@@ -393,9 +393,9 @@ SiteMask RegisterSite::nextWordMask(Context* c, unsigned)
   assertT(c, number != NoRegister);
 
   if (registerSize(c) > c->targetInfo.pointerSize) {
-    return SiteMask(1 << (unsigned)lir::Operand::Type::RegisterPair, number, NoFrameIndex);
+    return SiteMask(lir::Operand::RegisterPairMask, number, NoFrameIndex);
   } else {
-    return SiteMask(1 << (unsigned)lir::Operand::Type::RegisterPair,
+    return SiteMask(lir::Operand::RegisterPairMask,
                     c->regFile->generalRegisters,
                     NoFrameIndex);
   }
@@ -466,7 +466,7 @@ unsigned MemorySite::copyCost(Context* c, Site* s)
 
 bool MemorySite::conflicts(const SiteMask& mask)
 {
-  return (mask.typeMask & (1 << (unsigned)lir::Operand::Type::RegisterPair)) != 0
+  return (mask.typeMask & lir::Operand::RegisterPairMask) != 0
          and (!mask.registerMask.contains(base)
               or (index != NoRegister
                   and !mask.registerMask.contains(index)));
@@ -476,7 +476,7 @@ bool MemorySite::match(Context* c, const SiteMask& mask)
 {
   assertT(c, acquired);
 
-  if (mask.typeMask & (1 << (unsigned)lir::Operand::Type::Memory)) {
+  if (mask.typeMask & lir::Operand::MemoryMask) {
     if (mask.frameIndex >= 0) {
       if (base == c->arch->stack()) {
         assertT(c, index == NoRegister);
@@ -497,7 +497,7 @@ bool MemorySite::loneMatch(Context* c, const SiteMask& mask)
 {
   assertT(c, acquired);
 
-  if (mask.typeMask & (1 << (unsigned)lir::Operand::Type::Memory)) {
+  if (mask.typeMask & lir::Operand::MemoryMask) {
     if (base == c->arch->stack()) {
       assertT(c, index == NoRegister);
 
@@ -657,7 +657,7 @@ Site* MemorySite::makeNextWord(Context* c, unsigned index)
 
 SiteMask MemorySite::mask(Context* c)
 {
-  return SiteMask(1 << (unsigned)lir::Operand::Type::Memory,
+  return SiteMask(lir::Operand::MemoryMask,
                   0,
                   (base == c->arch->stack())
                       ? static_cast<int>(offsetToFrameIndex(c, offset))
@@ -674,7 +674,7 @@ SiteMask MemorySite::nextWordMask(Context* c, unsigned index)
   } else {
     frameIndex = NoFrameIndex;
   }
-  return SiteMask(1 << (unsigned)lir::Operand::Type::Memory, 0, frameIndex);
+  return SiteMask(lir::Operand::MemoryMask, 0, frameIndex);
 }
 
 bool MemorySite::isVolatile(Context* c)

src/codegen/compiler/site.h

@@ -43,7 +43,7 @@ class SiteMask {
 
   static SiteMask fixedRegisterMask(Register number)
   {
-    return SiteMask(1 << (unsigned)lir::Operand::Type::RegisterPair, 1 << (int8_t)number, NoFrameIndex);
+    return SiteMask(lir::Operand::RegisterPairMask, 1 << (int8_t)number, NoFrameIndex);
   }
 
   static SiteMask lowPart(const OperandMask& mask)
@@ -187,7 +187,7 @@ class ConstantSite : public Site {
 
   virtual bool match(Context*, const SiteMask& mask)
   {
-    return mask.typeMask & (1 << (unsigned)lir::Operand::Type::Constant);
+    return mask.typeMask & lir::Operand::ConstantMask;
   }
 
   virtual bool loneMatch(Context*, const SiteMask&)
@@ -236,12 +236,12 @@ class ConstantSite : public Site {
 
   virtual SiteMask mask(Context*)
   {
-    return SiteMask(1 << (unsigned)lir::Operand::Type::Constant, 0, NoFrameIndex);
+    return SiteMask(lir::Operand::ConstantMask, 0, NoFrameIndex);
   }
 
   virtual SiteMask nextWordMask(Context*, unsigned)
   {
-    return SiteMask(1 << (unsigned)lir::Operand::Type::Constant, 0, NoFrameIndex);
+    return SiteMask(lir::Operand::ConstantMask, 0, NoFrameIndex);
   }
 
   Promise* value;

src/codegen/target/arm/assembler.cpp

@@ -396,7 +396,7 @@ class MyArchitecture : public Architecture {
                     OperandMask& aMask,
                     bool* thunk)
   {
-    aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair) | (1 << (unsigned)lir::Operand::Type::Constant);
+    aMask.typeMask = lir::Operand::RegisterPairMask | lir::Operand::ConstantMask;
     aMask.setLowHighRegisterMasks(~static_cast<uint64_t>(0), ~static_cast<uint64_t>(0));
     *thunk = false;
   }
@@ -413,7 +413,7 @@ class MyArchitecture : public Architecture {
 
     switch (op) {
     case lir::Negate:
-      aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+      aMask.typeMask = lir::Operand::RegisterPairMask;
       aMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
       break;
 
@@ -426,7 +426,7 @@ class MyArchitecture : public Architecture {
     case lir::FloatNegate:
     case lir::Float2Float:
       if (vfpSupported()) {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+        aMask.typeMask = lir::Operand::RegisterPairMask;
         aMask.setLowHighRegisterMasks(FPR_MASK, FPR_MASK);
       } else {
         *thunk = true;
@@ -439,7 +439,7 @@ class MyArchitecture : public Architecture {
       // thunks or produce inline machine code which handles edge
       // cases properly.
       if (false && vfpSupported() && bSize == 4) {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+        aMask.typeMask = lir::Operand::RegisterPairMask;
         aMask.setLowHighRegisterMasks(FPR_MASK, FPR_MASK);
       } else {
         *thunk = true;
@@ -448,7 +448,7 @@ class MyArchitecture : public Architecture {
 
     case lir::Int2Float:
       if (vfpSupported() && aSize == 4) {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+        aMask.typeMask = lir::Operand::RegisterPairMask;
         aMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
       } else {
         *thunk = true;
@@ -466,12 +466,12 @@ class MyArchitecture : public Architecture {
                                unsigned,
                                OperandMask& bMask)
   {
-    bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair) | (1 << (unsigned)lir::Operand::Type::Memory);
+    bMask.typeMask = lir::Operand::RegisterPairMask | lir::Operand::MemoryMask;
     bMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
 
     switch (op) {
     case lir::Negate:
-      bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+      bMask.typeMask = lir::Operand::RegisterPairMask;
       bMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
       break;
 
@@ -480,18 +480,18 @@ class MyArchitecture : public Architecture {
     case lir::FloatNegate:
     case lir::Float2Float:
     case lir::Int2Float:
-      bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+      bMask.typeMask = lir::Operand::RegisterPairMask;
       bMask.setLowHighRegisterMasks(FPR_MASK, FPR_MASK);
       break;
 
     case lir::Float2Int:
-      bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+      bMask.typeMask = lir::Operand::RegisterPairMask;
       bMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
       break;
 
     case lir::Move:
-      if (!(aMask.typeMask & 1 << (unsigned)lir::Operand::Type::RegisterPair)) {
+      if (!(aMask.typeMask & lir::Operand::RegisterPairMask)) {
-        bMask.typeMask = 1 << (unsigned)lir::Operand::Type::RegisterPair;
+        bMask.typeMask = lir::Operand::RegisterPairMask;
       }
       break;
 
@@ -511,15 +511,15 @@ class MyArchitecture : public Architecture {
     tmpMask.typeMask = 0;
     tmpMask.setLowHighRegisterMasks(0, 0);
 
-    if (dstMask.typeMask & (1 << (unsigned)lir::Operand::Type::Memory)) {
+    if (dstMask.typeMask & lir::Operand::MemoryMask) {
       // can't move directly from memory or constant to memory
-      srcMask.typeMask = 1 << (unsigned)lir::Operand::Type::RegisterPair;
+      srcMask.typeMask = lir::Operand::RegisterPairMask;
-      tmpMask.typeMask = 1 << (unsigned)lir::Operand::Type::RegisterPair;
+      tmpMask.typeMask = lir::Operand::RegisterPairMask;
       tmpMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
-    } else if (vfpSupported() && dstMask.typeMask & 1 << (unsigned)lir::Operand::Type::RegisterPair
+    } else if (vfpSupported() && dstMask.typeMask & lir::Operand::RegisterPairMask
                && dstMask.lowRegisterMask & FPR_MASK) {
-      srcMask.typeMask = tmpMask.typeMask = 1 << (unsigned)lir::Operand::Type::RegisterPair
+      srcMask.typeMask = tmpMask.typeMask = lir::Operand::RegisterPairMask
-                                            | 1 << (unsigned)lir::Operand::Type::Memory;
+                                            | lir::Operand::MemoryMask;
       tmpMask.setLowHighRegisterMasks(~static_cast<uint64_t>(0), ~static_cast<uint64_t>(0));
     }
   }
@@ -532,10 +532,10 @@ class MyArchitecture : public Architecture {
                           unsigned,
                           bool* thunk)
   {
-    aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair) | (1 << (unsigned)lir::Operand::Type::Constant);
+    aMask.typeMask = lir::Operand::RegisterPairMask | lir::Operand::ConstantMask;
     aMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
 
-    bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+    bMask.typeMask = lir::Operand::RegisterPairMask;
     bMask.setLowHighRegisterMasks(GPR_MASK, GPR_MASK);
 
     *thunk = false;
@@ -545,7 +545,7 @@ class MyArchitecture : public Architecture {
     case lir::ShiftRight:
     case lir::UnsignedShiftRight:
       if (bSize == 8)
-        aMask.typeMask = bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+        aMask.typeMask = bMask.typeMask = lir::Operand::RegisterPairMask;
       break;
 
     case lir::Add:
@@ -553,7 +553,7 @@ class MyArchitecture : public Architecture {
     case lir::Or:
     case lir::Xor:
     case lir::Multiply:
-      aMask.typeMask = bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+      aMask.typeMask = bMask.typeMask = lir::Operand::RegisterPairMask;
       break;
 
     case lir::Divide:
@@ -567,7 +567,7 @@ class MyArchitecture : public Architecture {
     case lir::FloatMultiply:
     case lir::FloatDivide:
       if (vfpSupported()) {
-        bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+        bMask.typeMask = lir::Operand::RegisterPairMask;
         aMask.setLowHighRegisterMasks(FPR_MASK, FPR_MASK);
         bMask = aMask;
       } else {
@@ -586,7 +586,7 @@ class MyArchitecture : public Architecture {
     case lir::JumpIfFloatLessOrEqualOrUnordered:
     case lir::JumpIfFloatGreaterOrEqualOrUnordered:
       if (vfpSupported()) {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+        aMask.typeMask = lir::Operand::RegisterPairMask;
         aMask.setLowHighRegisterMasks(FPR_MASK, FPR_MASK);
         bMask = aMask;
       } else {
@@ -608,10 +608,10 @@ class MyArchitecture : public Architecture {
                                OperandMask& cMask)
   {
     if (isBranch(op)) {
-      cMask.typeMask = (1 << (unsigned)lir::Operand::Type::Constant);
+      cMask.typeMask = lir::Operand::ConstantMask;
       cMask.setLowHighRegisterMasks(0, 0);
     } else {
-      cMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+      cMask.typeMask = lir::Operand::RegisterPairMask;
       cMask.lowRegisterMask = bMask.lowRegisterMask;
       cMask.highRegisterMask = bMask.highRegisterMask;
     }

src/codegen/target/x86/assembler.cpp

@@ -501,8 +501,8 @@ class MyArchitecture : public Architecture {
                     OperandMask& aMask,
                     bool* thunk)
   {
-    aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair) | (1 << (unsigned)lir::Operand::Type::Memory)
+    aMask.typeMask = lir::Operand::RegisterPairMask | lir::Operand::MemoryMask
-                     | (1 << (unsigned)lir::Operand::Type::Constant);
+                     | lir::Operand::ConstantMask;
     *thunk = false;
   }
 
@@ -518,13 +518,13 @@ class MyArchitecture : public Architecture {
 
     switch (op) {
     case lir::Negate:
-      aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+      aMask.typeMask = lir::Operand::RegisterPairMask;
       aMask.setLowHighRegisterMasks(rax, rdx);
       break;
 
     case lir::Absolute:
       if (aSize <= TargetBytesPerWord) {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+        aMask.typeMask = lir::Operand::RegisterPairMask;
         aMask.setLowHighRegisterMasks(rax, 0);
       } else {
         *thunk = true;
@@ -533,7 +533,7 @@ class MyArchitecture : public Architecture {
 
     case lir::FloatAbsolute:
       if (useSSE(&c)) {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+        aMask.typeMask = lir::Operand::RegisterPairMask;
         aMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
       } else {
         *thunk = true;
@@ -543,7 +543,7 @@ class MyArchitecture : public Architecture {
     case lir::FloatNegate:
       // floatNegateRR does not support doubles
       if (useSSE(&c) and aSize == 4 and bSize == 4) {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+        aMask.typeMask = lir::Operand::RegisterPairMask;
         aMask.setLowHighRegisterMasks(FloatRegisterMask, 0);
       } else {
         *thunk = true;
@@ -552,8 +552,8 @@ class MyArchitecture : public Architecture {
 
     case lir::FloatSquareRoot:
       if (useSSE(&c)) {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair)
+        aMask.typeMask = lir::Operand::RegisterPairMask
-                         | (1 << (unsigned)lir::Operand::Type::Memory);
+                         | lir::Operand::MemoryMask;
         aMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
       } else {
         *thunk = true;
@@ -562,8 +562,8 @@ class MyArchitecture : public Architecture {
 
     case lir::Float2Float:
       if (useSSE(&c)) {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair)
+        aMask.typeMask = lir::Operand::RegisterPairMask
-                         | (1 << (unsigned)lir::Operand::Type::Memory);
+                         | lir::Operand::MemoryMask;
         aMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
       } else {
         *thunk = true;
@@ -576,8 +576,8 @@ class MyArchitecture : public Architecture {
       // thunks or produce inline machine code which handles edge
       // cases properly.
       if (false and useSSE(&c) and bSize <= TargetBytesPerWord) {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair)
+        aMask.typeMask = lir::Operand::RegisterPairMask
-                         | (1 << (unsigned)lir::Operand::Type::Memory);
+                         | lir::Operand::MemoryMask;
         aMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
       } else {
         *thunk = true;
@@ -586,8 +586,8 @@ class MyArchitecture : public Architecture {
 
     case lir::Int2Float:
       if (useSSE(&c) and aSize <= TargetBytesPerWord) {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair)
+        aMask.typeMask = lir::Operand::RegisterPairMask
-                         | (1 << (unsigned)lir::Operand::Type::Memory);
+                         | lir::Operand::MemoryMask;
         aMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
       } else {
         *thunk = true;
@@ -600,14 +600,14 @@ class MyArchitecture : public Architecture {
 
       if (TargetBytesPerWord == 4) {
         if (aSize == 4 and bSize == 8) {
-          aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair)
+          aMask.typeMask = lir::Operand::RegisterPairMask
-                           | (1 << (unsigned)lir::Operand::Type::Memory);
+                           | lir::Operand::MemoryMask;
           const RegisterMask mask = GeneralRegisterMask
                                 .excluding(rax).excluding(rdx);
           aMask.setLowHighRegisterMasks(mask, mask);
         } else if (aSize == 1 or bSize == 1) {
-          aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair)
+          aMask.typeMask = lir::Operand::RegisterPairMask
-                           | (1 << (unsigned)lir::Operand::Type::Memory);
+                           | lir::Operand::MemoryMask;
           const RegisterMask mask = rax | rcx | rdx | rbx;
           aMask.setLowHighRegisterMasks(mask, mask);
         }
@@ -630,18 +630,18 @@ class MyArchitecture : public Architecture {
 
     switch (op) {
     case lir::Absolute:
-      bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+      bMask.typeMask = lir::Operand::RegisterPairMask;
       bMask.setLowHighRegisterMasks(rax, 0);
       break;
 
     case lir::FloatAbsolute:
-      bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+      bMask.typeMask = lir::Operand::RegisterPairMask;
       bMask.lowRegisterMask = aMask.lowRegisterMask;
       bMask.highRegisterMask = aMask.highRegisterMask;
       break;
 
     case lir::Negate:
-      bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+      bMask.typeMask = lir::Operand::RegisterPairMask;
       bMask.lowRegisterMask = aMask.lowRegisterMask;
       bMask.highRegisterMask = aMask.highRegisterMask;
       break;
@@ -650,30 +650,30 @@ class MyArchitecture : public Architecture {
     case lir::FloatSquareRoot:
     case lir::Float2Float:
     case lir::Int2Float:
-      bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+      bMask.typeMask = lir::Operand::RegisterPairMask;
       bMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
       break;
 
     case lir::Float2Int:
-      bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+      bMask.typeMask = lir::Operand::RegisterPairMask;
       break;
 
     case lir::Move:
       if (aMask.typeMask
-          & ((1 << (unsigned)lir::Operand::Type::Memory) | 1 << (unsigned)lir::Operand::Type::Address)) {
+          & (lir::Operand::MemoryMask | lir::Operand::AddressMask)) {
-        bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+        bMask.typeMask = lir::Operand::RegisterPairMask;
         bMask.setLowHighRegisterMasks(GeneralRegisterMask | FloatRegisterMask, GeneralRegisterMask);
-      } else if (aMask.typeMask & (1 << (unsigned)lir::Operand::Type::RegisterPair)) {
+      } else if (aMask.typeMask & lir::Operand::RegisterPairMask) {
-        bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair)
+        bMask.typeMask = lir::Operand::RegisterPairMask
-                         | (1 << (unsigned)lir::Operand::Type::Memory);
+                         | lir::Operand::MemoryMask;
         if (aMask.lowRegisterMask & FloatRegisterMask) {
           bMask.setLowHighRegisterMasks(FloatRegisterMask, 0);
         } else {
           bMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
         }
       } else {
-        bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair)
+        bMask.typeMask = lir::Operand::RegisterPairMask
-                         | (1 << (unsigned)lir::Operand::Type::Memory);
+                         | lir::Operand::MemoryMask;
       }
 
       if (TargetBytesPerWord == 4) {
@@ -702,32 +702,32 @@ class MyArchitecture : public Architecture {
     tmpMask.typeMask = 0;
     tmpMask.setLowHighRegisterMasks(0, 0);
 
-    if (dstMask.typeMask & (1 << (unsigned)lir::Operand::Type::Memory)) {
+    if (dstMask.typeMask & lir::Operand::MemoryMask) {
       // can't move directly from memory to memory
-      srcMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair)
+      srcMask.typeMask = lir::Operand::RegisterPairMask
-                         | (1 << (unsigned)lir::Operand::Type::Constant);
+                         | lir::Operand::ConstantMask;
-      tmpMask.typeMask = 1 << (unsigned)lir::Operand::Type::RegisterPair;
+      tmpMask.typeMask = lir::Operand::RegisterPairMask;
       tmpMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
-    } else if (dstMask.typeMask & (1 << (unsigned)lir::Operand::Type::RegisterPair)) {
+    } else if (dstMask.typeMask & lir::Operand::RegisterPairMask) {
       if (size > TargetBytesPerWord) {
         // can't move directly from FPR to GPR or vice-versa for
         // values larger than the GPR size
         if (dstMask.lowRegisterMask & FloatRegisterMask) {
           srcMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
-          tmpMask.typeMask = 1 << (unsigned)lir::Operand::Type::Memory;
+          tmpMask.typeMask = lir::Operand::MemoryMask;
         } else if (dstMask.lowRegisterMask & GeneralRegisterMask) {
           srcMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
-          tmpMask.typeMask = 1 << (unsigned)lir::Operand::Type::Memory;
+          tmpMask.typeMask = lir::Operand::MemoryMask;
         }
       }
       if (dstMask.lowRegisterMask & FloatRegisterMask) {
         // can't move directly from constant to FPR
-        srcMask.typeMask &= ~(1 << (unsigned)lir::Operand::Type::Constant);
+        srcMask.typeMask &= ~lir::Operand::ConstantMask;
         if (size > TargetBytesPerWord) {
-          tmpMask.typeMask = 1 << (unsigned)lir::Operand::Type::Memory;
+          tmpMask.typeMask = lir::Operand::MemoryMask;
         } else {
-          tmpMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair)
+          tmpMask.typeMask = lir::Operand::RegisterPairMask
-                             | (1 << (unsigned)lir::Operand::Type::Memory);
+                             | lir::Operand::MemoryMask;
           tmpMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
         }
       }
@@ -742,10 +742,10 @@ class MyArchitecture : public Architecture {
                           unsigned,
                           bool* thunk)
   {
-    aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair) | (1 << (unsigned)lir::Operand::Type::Constant);
+    aMask.typeMask = lir::Operand::RegisterPairMask | lir::Operand::ConstantMask;
     aMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
 
-    bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+    bMask.typeMask = lir::Operand::RegisterPairMask;
     bMask.setLowHighRegisterMasks(GeneralRegisterMask, GeneralRegisterMask);
 
     *thunk = false;
@@ -756,9 +756,9 @@ class MyArchitecture : public Architecture {
     case lir::FloatMultiply:
     case lir::FloatDivide:
       if (useSSE(&c)) {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair)
+        aMask.typeMask = lir::Operand::RegisterPairMask
-                         | (1 << (unsigned)lir::Operand::Type::Memory);
+                         | lir::Operand::MemoryMask;
-        bMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+        bMask.typeMask = lir::Operand::RegisterPairMask;
 
         aMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
         bMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
@@ -786,7 +786,7 @@ class MyArchitecture : public Architecture {
       if (TargetBytesPerWord == 4 and aSize == 8) {
         *thunk = true;
       } else {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+        aMask.typeMask = lir::Operand::RegisterPairMask;
         aMask.setLowHighRegisterMasks(GeneralRegisterMask .excluding(rax).excluding(rdx), 0);
         bMask.setLowHighRegisterMasks(rax, 0);
       }
@@ -796,7 +796,7 @@ class MyArchitecture : public Architecture {
       if (TargetBytesPerWord == 4 and aSize == 8) {
         *thunk = true;
       } else {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+        aMask.typeMask = lir::Operand::RegisterPairMask;
         aMask.setLowHighRegisterMasks(GeneralRegisterMask .excluding(rax).excluding(rdx), 0);
         bMask.setLowHighRegisterMasks(rax, 0);
       }
@@ -827,7 +827,7 @@ class MyArchitecture : public Architecture {
     case lir::JumpIfFloatLessOrEqualOrUnordered:
     case lir::JumpIfFloatGreaterOrEqualOrUnordered:
       if (useSSE(&c)) {
-        aMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+        aMask.typeMask = lir::Operand::RegisterPairMask;
         aMask.setLowHighRegisterMasks(FloatRegisterMask, FloatRegisterMask);
         bMask.typeMask = aMask.typeMask;
         bMask.lowRegisterMask = aMask.lowRegisterMask;
@@ -851,10 +851,10 @@ class MyArchitecture : public Architecture {
                                OperandMask& cMask)
   {
     if (isBranch(op)) {
-      cMask.typeMask = (1 << (unsigned)lir::Operand::Type::Constant);
+      cMask.typeMask = lir::Operand::ConstantMask;
       cMask.setLowHighRegisterMasks(0, 0);
     } else {
-      cMask.typeMask = (1 << (unsigned)lir::Operand::Type::RegisterPair);
+      cMask.typeMask = lir::Operand::RegisterPairMask;
       cMask.lowRegisterMask = bMask.lowRegisterMask;
       cMask.highRegisterMask = bMask.highRegisterMask;
     }