mirror of
https://github.com/Nuand/bladeRF-wiphy.git
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98 lines
2.7 KiB
VHDL
98 lines
2.7 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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package nco_p is
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type nco_input_t is record
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dphase : signed(15 downto 0) ;
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valid : std_logic ;
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end record ;
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type nco_output_t is record
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re : signed(15 downto 0) ;
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im : signed(15 downto 0) ;
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valid : std_logic ;
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end record ;
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end package ; -- nco_p
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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library work ;
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use work.cordic_p.all ;
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use work.nco_p.all ;
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entity nco is
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port (
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clock : in std_logic ;
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reset : in std_logic ;
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inputs : in nco_input_t ;
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outputs : out nco_output_t
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) ;
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end entity ; -- nco
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architecture arch of nco is
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signal phase : signed(15 downto 0) ;
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signal cordic_inputs : cordic_xyz_t ;
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signal cordic_outputs : cordic_xyz_t ;
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begin
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accumulate_phase : process(clock, reset)
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variable temp : signed(15 downto 0) ;
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begin
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if( reset = '1' ) then
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phase <= (others =>'0') ;
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elsif( rising_edge( clock ) ) then
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if( inputs.valid = '1' ) then
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temp := phase + inputs.dphase ;
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if( temp > 16384 ) then
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temp := temp - 32768 ;
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elsif( temp < -16384 ) then
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temp := temp + 32768 ;
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end if ;
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phase <= temp ;
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end if ;
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end if ;
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end process ;
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cordic_inputs <= ( x => to_signed(1234,16), y => to_signed(0,16), z => phase, valid => inputs.valid ) ;
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U_cordic : entity work.cordic
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port map (
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clock => clock,
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reset => reset,
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mode => CORDIC_ROTATION,
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inputs => cordic_inputs,
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outputs => cordic_outputs
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) ;
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outputs.re <= cordic_outputs.x ;
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outputs.im <= cordic_outputs.y ;
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outputs.valid <= cordic_outputs.valid ;
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end architecture ; -- arch
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