mirror of
https://github.com/Nuand/bladeRF-wiphy.git
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229 lines
8.1 KiB
VHDL
229 lines
8.1 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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library wlan ;
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use wlan.wlan_p.all ;
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use wlan.wlan_rx_p.all ;
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entity wlan_rx_controller is
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port (
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clock : in std_logic ;
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reset : in std_logic ;
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framer_quiet_reset: out std_logic ;
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params : in wlan_rx_params_t ;
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params_valid : in std_logic ;
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sample_valid : in std_logic ;
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end_of_packet : out std_logic ;
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rx_packet_init : out std_logic ;
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rx_quiet : in std_logic ;
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rx_framer_done : in std_logic ;
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acquired : in std_logic ;
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p_mag : in signed( 23 downto 0 ) ;
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atan_average : in signed( 15 downto 0 ) ;
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c_dphase : out signed( 15 downto 0 ) ;
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c_dphase_valid : out std_logic ;
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c_p_mag : out signed( 23 downto 0 ) ;
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c_p_mag_valid : out std_logic ;
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symbol_start : out std_logic
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) ;
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end entity;
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architecture arch of wlan_rx_controller is
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type fsm_t is (ACQUIRING, INIT_EQ, WAIT_FOR_CFO, DEC_SIGNAL, DEMOD, WAIT_EOP) ;
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type state_t is record
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fsm : fsm_t ;
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pkt_time : unsigned( 23 downto 0 ) ;
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sym_time : unsigned( 23 downto 0 ) ;
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c_dphase : signed( 15 downto 0 ) ;
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c_dphase_valid : std_logic ;
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c_p_mag : signed( 23 downto 0 ) ;
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c_p_mag_valid : std_logic ;
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end_of_packet : std_logic ;
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packet_init : std_logic ;
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symbol_start : std_logic ;
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decoded_bits : natural range 0 to 12000 ;
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bit_index : natural range 0 to 12000 ;
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n_dbps : natural range 24 to 216 ;
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symbol_count : natural range 0 to 1366 ;
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symbol_index : natural range 0 to 1366 ;
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framer_reset : std_logic ;
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end record ;
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function NULL_STATE return state_t is
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variable rv : state_t ;
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begin
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rv.fsm := ACQUIRING ;
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rv.pkt_time := ( others => '0' );
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rv.c_dphase := ( others => '0' ) ;
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rv.c_dphase_valid := '0' ;
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rv.c_p_mag := ( others => '0' ) ;
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rv.c_p_mag_valid := '0' ;
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rv.end_of_packet := '0' ;
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rv.packet_init := '0' ;
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rv.symbol_start := '0' ;
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rv.decoded_bits := 0 ;
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rv.bit_index := 0 ;
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rv.n_dbps := 24 ;
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rv.symbol_count := 0 ;
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rv.symbol_index := 0 ;
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rv.framer_reset := '1' ;
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return rv ;
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end function ;
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signal current, future : state_t := NULL_STATE ;
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begin
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rx_packet_init <= current.packet_init ;
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c_dphase <= current.c_dphase ;
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c_dphase_valid <= current.c_dphase_valid ;
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c_p_mag <= current.c_p_mag ;
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c_p_mag_valid <= current.c_p_mag_valid ;
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symbol_start <= current.symbol_start ;
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end_of_packet <= current.end_of_packet ;
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framer_quiet_reset <= current.framer_reset ;
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sync : process( clock )
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begin
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if( reset = '1' ) then
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current <= NULL_STATE ;
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elsif( rising_edge( clock ) ) then
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current <= future ;
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end if ;
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end process ;
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comb: process(all)
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begin
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future <= current ;
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future.symbol_start <= '0' ;
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future.packet_init <= '0' ;
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case current.fsm is
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when ACQUIRING =>
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if( acquired = '1' ) then
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-- it takes the acquisition core 201 samples after the actual
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-- start of packet until it asserts acquired
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future.pkt_time <= to_unsigned( 212+1, future.pkt_time'length ) ;
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future.c_p_mag <= p_mag ;
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future.c_p_mag_valid <= '1' ;
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future.fsm <= INIT_EQ ;
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future.symbol_index <= 1 ;
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future.symbol_count <= 0 ;
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future.packet_init <= '1' ;
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future.framer_reset <= '0' ;
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else
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future <= NULL_STATE ;
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end if ;
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when INIT_EQ =>
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if( rx_quiet = '1' ) then
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future.fsm <= ACQUIRING ;
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end if ;
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if( sample_valid = '1' ) then
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future.pkt_time <= current.pkt_time + 1 ;
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if( current.pkt_time = 256 ) then
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future.symbol_start <= '1' ;
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future.fsm <= WAIT_FOR_CFO ;
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end if ;
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end if ;
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when WAIT_FOR_CFO =>
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if( rx_quiet = '1' ) then
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future.fsm <= ACQUIRING ;
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end if ;
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if( sample_valid = '1' ) then
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future.pkt_time <= current.pkt_time + 1 ;
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if( current.pkt_time > 300 ) then
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future.c_dphase <= shift_right( - atan_average, 6 ) ;
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future.c_dphase_valid <= '1' ;
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future.sym_time <= to_unsigned(336, future.sym_time'length);
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future.fsm <= DEC_SIGNAL ;
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end if ;
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end if ;
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when DEC_SIGNAL =>
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if( rx_quiet = '1' ) then
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future.fsm <= ACQUIRING ;
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future.end_of_packet <= '1' ;
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end if ;
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if( params_valid = '1' ) then
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if( params.packet_valid = '1' ) then
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future.decoded_bits <= params.num_data_symbols ;
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future.n_dbps <= params.n_dbps ;
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future.bit_index <= params.n_dbps ;
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future.fsm <= DEMOD ;
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else
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future.fsm <= ACQUIRING ;
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future.end_of_packet <= '1' ;
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end if ;
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end if ;
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if( sample_valid = '1' ) then
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future.pkt_time <= current.pkt_time + 1 ;
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if( current.sym_time = current.pkt_time) then
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future.sym_time <= current.sym_time + 80;
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future.symbol_start <= '1' ;
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end if ;
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end if ;
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when DEMOD =>
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if( rx_quiet = '1' ) then
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future.fsm <= ACQUIRING ;
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future.end_of_packet <= '1' ;
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elsif( sample_valid = '1' ) then
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future.pkt_time <= current.pkt_time + 1 ;
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if( current.pkt_time = current.sym_time ) then
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future.sym_time <= current.sym_time + 80;
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future.bit_index <= current.bit_index + current.n_dbps ;
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future.symbol_start <= '1' ;
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end if ;
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if (current.bit_index >= current.decoded_bits ) then
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future.sym_time <= to_unsigned(5000, future.sym_time'length);
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future.fsm <= WAIT_EOP ;
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end if ;
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end if ;
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when WAIT_EOP =>
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if( rx_framer_done = '1' or current.sym_time = 0) then
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future.fsm <= ACQUIRING ;
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future.end_of_packet <= '1' ;
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end if ;
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future.sym_time <= current.sym_time - 1 ;
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when others =>
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future.fsm <= ACQUIRING ;
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end case ;
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end process ;
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end architecture ;
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