mirror of
https://github.com/Nuand/bladeRF-wiphy.git
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141 lines
3.7 KiB
VHDL
141 lines
3.7 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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library wlan ;
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use wlan.nco_p.all ;
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use wlan.wlan_p.all ;
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use wlan.wlan_rx_p.all ;
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library altera_mf ;
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use altera_mf.altera_mf_components.all ;
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library wlan_pll ;
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entity wlan_dsss_rx is
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port (
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-- 40MHz clock and async asserted, sync deasserted reset
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clock : in std_logic ;
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reset : in std_logic ;
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-- Baseband input signals
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sample : in wlan_sample_t ;
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params : out wlan_rx_params_t ;
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params_valid : out std_logic ;
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data : out std_logic_vector( 7 downto 0 ) ;
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data_valid : out std_logic ;
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framer_done : out std_logic ;
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crc_correct : out std_logic
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) ;
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end entity ;
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architecture arch of wlan_dsss_rx is
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signal despread : wlan_sample_t ;
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signal p_norm_sample : wlan_sample_t ;
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signal modulation : wlan_modulation_t ;
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signal bin_idx : natural range 0 to 20 ;
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signal mode_bin : natural range 0 to 20 ;
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signal demod_bits : std_logic_vector( 1 downto 0 ) ;
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signal demod_idx : natural range 0 to 20 ;
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signal demod_valid : std_logic ;
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begin
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U_dsss_rx_controller : entity work.wlan_dsss_rx_controller
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port map (
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clock => clock,
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reset => reset,
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in_sample => sample,
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modulation => modulation,
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out_bin_idx => bin_idx
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) ;
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U_dsss_p_norm : entity work.wlan_dsss_p_norm
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port map (
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clock => clock,
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reset => reset,
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in_sample => sample,
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p_normed => p_norm_sample
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) ;
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U_dsss_despreader : entity work.wlan_dsss_despreader
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port map (
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clock => clock,
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reset => reset,
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sample => p_norm_sample,
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despread => despread
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) ;
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U_dsss_peak_finder : entity work.wlan_dsss_peak_finder
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port map (
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clock => clock,
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reset => reset,
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despread => despread,
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bin_idx => bin_idx,
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out_mode_bin => mode_bin
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) ;
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U_dsss_demodulator : entity work.wlan_dsss_demodulator
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port map (
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clock => clock,
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reset => reset,
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modulation => modulation,
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in_bin_idx => bin_idx,
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despread => despread,
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out_bin_idx => demod_idx,
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out_bits => demod_bits,
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out_valid => demod_valid
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) ;
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U_dsss_rx_framer : entity work.wlan_dsss_rx_framer
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port map (
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clock => clock,
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reset => reset,
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mode_bin => mode_bin,
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demod_idx => demod_idx,
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demod_bits => demod_bits,
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demod_valid => demod_valid,
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params => params,
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params_valid => params_valid,
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data => data,
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data_valid => data_valid,
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framer_done => framer_done,
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crc_correct => crc_correct
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) ;
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end architecture ;
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