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https://github.com/Nuand/bladeRF-wiphy.git
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107 lines
3.5 KiB
VHDL
107 lines
3.5 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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library lpm ;
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use lpm.lpm_components.all ;
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entity wlan_divide is
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generic (
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SAMPLE_WIDTH : natural ;
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DENOM_WIDTH : natural ;
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NUM_PIPELINE : natural
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) ;
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port (
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clock : in std_logic ;
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reset : in std_logic ;
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in_i : in signed(SAMPLE_WIDTH-1 downto 0) ;
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in_q : in signed(SAMPLE_WIDTH-1 downto 0) ;
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in_denom : in unsigned(DENOM_WIDTH-1 downto 0) ;
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in_valid : in std_logic ;
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in_done : in std_logic ;
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out_i : out signed(SAMPLE_WIDTH-1 downto 0) ;
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out_q : out signed(SAMPLE_WIDTH-1 downto 0) ;
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out_valid : out std_logic ;
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out_done : out std_logic
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) ;
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end entity ;
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architecture altera of wlan_divide is
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signal done : std_logic_vector(NUM_PIPELINE-1 downto 0) ;
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signal valid : std_logic_vector(NUM_PIPELINE-1 downto 0) ;
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begin
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register_valids_and_done : process(clock, reset)
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begin
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if( reset = '1' ) then
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done <= (others =>'0') ;
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valid <= (others =>'0') ;
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elsif( rising_edge(clock) ) then
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done <= done(done'high-1 downto 0) & in_done ;
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valid <= valid(valid'high-1 downto 0) & in_valid ;
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end if ;
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end process ;
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out_done <= done(done'high) ;
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out_valid <= valid(valid'high) ;
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div_i : lpm_divide
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generic map (
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lpm_nrepresentation => "SIGNED",
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lpm_drepresentation => "UNSIGNED",
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lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
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lpm_pipeline => NUM_PIPELINE,
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lpm_type => "LPM_DIVIDE",
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lpm_widthd => DENOM_WIDTH,
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lpm_widthn => SAMPLE_WIDTH
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) port map (
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clock => clock,
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aclr => reset,
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numer => std_logic_vector(in_i),
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denom => std_logic_vector(in_denom),
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remain => open,
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signed(quotient) => out_i
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) ;
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div_q : lpm_divide
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generic map (
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lpm_nrepresentation => "SIGNED",
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lpm_drepresentation => "UNSIGNED",
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lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
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lpm_pipeline => NUM_PIPELINE,
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lpm_type => "LPM_DIVIDE",
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lpm_widthd => DENOM_WIDTH,
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lpm_widthn => SAMPLE_WIDTH
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) port map (
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clock => clock,
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aclr => reset,
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numer => std_logic_vector(in_q),
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denom => std_logic_vector(in_denom),
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remain => open,
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signed(quotient) => out_q
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) ;
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end architecture ;
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