mirror of
https://github.com/Nuand/bladeRF-wiphy.git
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244 lines
8.0 KiB
VHDL
244 lines
8.0 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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use ieee.math_real.all ;
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use ieee.math_complex.all ;
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library work ;
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use work.wlan_p.all ;
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use work.wlan_interleaver_p.all ;
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use work.wlan_rx_p.all ;
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entity wlan_demodulator is
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port (
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clock : in std_logic ;
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reset : in std_logic ;
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init : in std_logic ;
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params : in wlan_rx_params_t ;
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params_valid : in std_logic ;
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in_sample : in wlan_sample_t ;
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in_done : in std_logic ;
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dfe_sample : out wlan_sample_t ;
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out_mod : out wlan_modulation_t ;
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out_data : out bsd_array_t( 287 downto 0 ) ;
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out_valid : out std_logic
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) ;
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end entity ;
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architecture arch of wlan_demodulator is
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type fsm_t is (IDLE, DEMODULATING) ;
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type bsd_fsm_t is (IDLE, DEMODULATING) ;
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type state_t is record
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fsm : fsm_t ;
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bsds : bsd_array_t(287 downto 0) ;
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index : natural range 0 to 70 ;
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modulation : wlan_modulation_t ;
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dfe : wlan_sample_t ;
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valid : std_logic ;
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pilot_polarity : std_logic ;
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lfsr_advance : std_logic ;
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end record ;
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function NULL_STATE return state_t is
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variable rv : state_t ;
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begin
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rv.fsm := IDLE ;
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rv.bsds := (others =>( others => '0' )) ;
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rv.index := 0 ;
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rv.modulation := WLAN_BPSK ;
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rv.valid := '0' ;
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rv.pilot_polarity := '1' ;
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rv.lfsr_advance := '0' ;
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return rv ;
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end function ;
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-- TODO: Add in the pilot polarity LFSR
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function reorder_bsds( x : bsd_array_t(287 downto 0) ; modulation : wlan_modulation_t ) return bsd_array_t is
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variable rv : bsd_array_t(287 downto 0) ;
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begin
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rv := ( others => (others => '0' ) );
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-- Positions 24 -> 47 come first (positive frequencies)
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-- Positions 0 -> 23 are reversed and come afterwards (negative frequencies)
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case modulation is
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when WLAN_BPSK =>
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rv(24*1-1 downto 0) := x(48*1-1 downto 24*1) ;
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rv(48*1-1 downto 24*1) := x(24*1-1 downto 0) ;
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when WLAN_QPSK =>
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rv(24*2-1 downto 0) := x(48*2-1 downto 24*2) ;
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rv(48*2-1 downto 24*2) := x(24*2-1 downto 0) ;
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when WLAN_16QAM =>
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rv(24*4-1 downto 0) := x(48*4-1 downto 24*4) ;
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rv(48*4-1 downto 24*4) := x(24*4-1 downto 0) ;
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when WLAN_64QAM =>
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rv(24*6-1 downto 0) := x(48*6-1 downto 24*6) ;
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rv(48*6-1 downto 24*6) := x(24*6-1 downto 0) ;
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when others =>
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end case ;
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return rv ;
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end function ;
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signal current, future : state_t := NULL_STATE ;
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signal out_sample : wlan_sample_t ;
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signal clamped : wlan_sample_t ;
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signal lfsr_data : std_logic_vector( 0 downto 0 ) ;
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signal lfsr_advance : std_logic ;
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signal bsdd_bsds : wlan_bsds_t ;
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begin
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dfe_sample.i <= resize( shift_left(clamped.i, 0), 16 ) ;
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dfe_sample.q <= resize( shift_left(clamped.q, 0), 16 ) ;
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dfe_sample.valid <= '0' ; --clamped.valid ;
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u_bsd : entity work.wlan_bsd
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port map(
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clock => clock,
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reset => reset,
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modulation => params.modulation,
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in_sample => in_sample,
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out_sample => out_sample,
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bsds => bsdd_bsds
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);
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u_clampler : entity work.wlan_clamper
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port map(
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clock => clock,
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reset => reset,
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in_mod => params.modulation,
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in_ssd => in_sample,
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out_ssd => open,
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out_clamped => clamped,
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out_error => open
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);
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lfsr_advance <= current.lfsr_advance ;
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U_lfsr : entity work.wlan_lfsr
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generic map (
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WIDTH => lfsr_data'length
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) port map (
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clock => clock,
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reset => reset,
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init => (others =>'1'),
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init_valid => init,
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advance => lfsr_advance,
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data => lfsr_data,
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data_valid => open
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) ;
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sync : process(clock, reset)
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begin
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if( reset = '1' ) then
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current <= NULL_STATE ;
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elsif( rising_edge(clock) ) then
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if( current.fsm /= IDLE and init = '1' ) then
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current <= NULL_STATE ;
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else
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current <= future ;
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end if ;
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end if ;
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end process ;
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out_mod <= current.modulation ;
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out_data <= current.bsds ;
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out_valid <= current.valid ;
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comb : process(all)
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variable tmp_bsds : bsd_array_t(287 downto 0) ;
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begin
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future <= current ;
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future.valid <= '0' ;
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future.lfsr_advance <= '0' ;
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if( params_valid = '1' ) then
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future.modulation <= params.modulation ;
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end if ;
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future.pilot_polarity <= lfsr_data(0);
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case current.fsm is
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when IDLE =>
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future.modulation <= WLAN_BPSK ;
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future.fsm <= DEMODULATING ;
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when DEMODULATING =>
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if( bsdd_bsds.valid = '1' ) then
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case current.index is
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-- Check for DC null
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when 0 =>
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-- Check for outside nulls
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when 27 to 37 =>
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-- Check for 3 positive pilots
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when 7|43|57 =>
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-- Check for 1 negative pilot
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when 21 =>
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-- Otherwise data
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when others =>
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case current.modulation is
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when WLAN_BPSK =>
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future.bsds <= current.bsds(287 downto 48) & bsdd_bsds.bsds(0) & current.bsds(47 downto 1);
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when WLAN_QPSK =>
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future.bsds <= current.bsds(287 downto 96) & bsdd_bsds.bsds(1 downto 0) & current.bsds(95 downto 2);
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when WLAN_16QAM =>
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future.bsds <= current.bsds(287 downto 192) & bsdd_bsds.bsds(3 downto 0) & current.bsds(191 downto 4);
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when WLAN_64QAM =>
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future.bsds <= bsdd_bsds.bsds( 5 downto 0) & current.bsds(287 downto 6);
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when others =>
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end case ;
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end case ;
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-- Check if we've reached a full symbol length
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if( current.index < 64 ) then
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future.index <= current.index + 1 ;
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end if ;
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end if ;
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if( current.index = 64) then
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future.lfsr_advance <= '1' ;
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future.index <= 0 ;
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future.bsds <= reorder_bsds(current.bsds, current.modulation) ;
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future.valid <= '1' ;
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end if ;
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end case ;
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end process ;
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end architecture ;
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