mirror of
https://github.com/Nuand/bladeRF-wiphy.git
synced 2024-12-19 05:38:09 +00:00
93 lines
3.8 KiB
VHDL
93 lines
3.8 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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library wlan ;
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use wlan.wlan_p.all ;
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use wlan.wlan_rx_p.all ;
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entity wlan_correlator is
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port (
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clock : in std_logic ;
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reset : in std_logic ;
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sample : in wlan_sample_t ;
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value : out signed( 31 downto 0 )
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) ;
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end entity ;
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architecture arch of wlan_correlator is
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constant preamble : sample_array_t( 15 downto 0 ) := (
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(valid => '1', i => to_signed( 269, 16), q => to_signed( 269, 16)),
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(valid => '1', i => to_signed(-775, 16), q => to_signed( 14, 16)),
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(valid => '1', i => to_signed( -79, 16), q => to_signed(-460, 16)),
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(valid => '1', i => to_signed( 835, 16), q => to_signed( -74, 16)),
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(valid => '1', i => to_signed( 538, 16), q => to_signed( 0, 16)),
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(valid => '1', i => to_signed( 835, 16), q => to_signed( -74, 16)),
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(valid => '1', i => to_signed( -79, 16), q => to_signed(-460, 16)),
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(valid => '1', i => to_signed(-775, 16), q => to_signed( 14, 16)),
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(valid => '1', i => to_signed( 269, 16), q => to_signed( 269, 16)),
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(valid => '1', i => to_signed( 14, 16), q => to_signed(-775, 16)),
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(valid => '1', i => to_signed(-460, 16), q => to_signed( -79, 16)),
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(valid => '1', i => to_signed( -74, 16), q => to_signed( 835, 16)),
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(valid => '1', i => to_signed( 0, 16), q => to_signed( 538, 16)),
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(valid => '1', i => to_signed( -74, 16), q => to_signed( 835, 16)),
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(valid => '1', i => to_signed(-460, 16), q => to_signed( -79, 16)),
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(valid => '1', i => to_signed( 14, 16), q => to_signed(-775, 16))
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);
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type correlator_result_t is record
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i : signed(15 downto 0) ;
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q : signed(15 downto 0) ;
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valid : std_logic ;
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end record ;
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type eq_array_t is array(natural range <>) of correlator_result_t ;
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signal accum : eq_array_t(15 downto 0);
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begin
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process( clock )
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variable isum : signed( 100 downto 0 ) ;
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variable qsum : signed( 100 downto 0 ) ;
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begin
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if( reset = '1' ) then
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value <= ( others => '0' ) ;
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elsif( rising_edge( clock ) ) then
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if( sample.valid = '1' ) then
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for i in accum'range loop
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if i = accum'high then
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accum(i).i <= resize(shift_right(preamble(i).i*sample.i + preamble(i).q*sample.q, 14),16);
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accum(i).q <= resize(shift_right(- preamble(i).q*sample.i + preamble(i).i*sample.q, 14),16);
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else
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accum(i).i <= resize(accum(i+1).i + shift_right(preamble(i).i*sample.i + preamble(i).q*sample.q, 14),16);
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accum(i).q <= resize(accum(i+1).q + shift_right(- preamble(i).q*sample.i + preamble(i).i*sample.q, 14),16);
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end if;
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end loop;
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value <= resize(accum(0).i * accum(0).i + accum(0).q * accum(0).q,32);
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end if ;
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end if ;
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end process ;
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end architecture ;
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