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61 lines
1.9 KiB
VHDL
61 lines
1.9 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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library wlan ;
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use wlan.wlan_rx_p.all ;
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entity clock_sync_logic_vector is
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generic (
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LEN : integer := 8
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) ;
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port (
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from_signal : in std_logic_vector(LEN-1 downto 0) ;
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to_clock : in std_logic ;
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to_reset : in std_logic ;
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to_signal : out std_logic_vector(LEN-1 downto 0)
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) ;
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end entity;
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architecture arch of clock_sync_logic_vector is
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signal t_sig_r : std_logic_vector(LEN-1 downto 0) ;
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attribute ALTERA_ATTRIBUTE : string;
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attribute ALTERA_ATTRIBUTE of arch: architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers *clock_sync_logic_vector|*_r* ] "" ";
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begin
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process(all)
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begin
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if( to_reset = '1' ) then
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t_sig_r <= ( others => '0' ) ;
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to_signal <= ( others => '0' ) ;
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elsif( rising_edge( to_clock ) ) then
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t_sig_r <= from_signal ;
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to_signal <= t_sig_r ;
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end if ;
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end process ;
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end architecture ;
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