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https://github.com/Nuand/bladeRF-wiphy.git
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63 lines
1.9 KiB
VHDL
63 lines
1.9 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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library work ;
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use work.wlan_p.all ;
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use work.wlan_interleaver_p.all ;
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entity wlan_interleaver is
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port (
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clock : in std_logic ;
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reset : in std_logic ;
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modulation : in wlan_modulation_t ;
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data : in std_logic_vector(287 downto 0) ;
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in_valid : in std_logic ;
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interleaved : out std_logic_vector(287 downto 0) ;
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interleaved_mod : out wlan_modulation_t ;
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interleaved_valid : out std_logic
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) ;
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end entity ;
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architecture arch of wlan_interleaver is
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begin
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permute_bits : process(clock, reset)
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begin
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if( reset = '1' ) then
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interleaved <= (others =>'0') ;
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interleaved_mod <= WLAN_BPSK ;
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interleaved_valid <= '0' ;
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elsif( rising_edge(clock) ) then
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interleaved_valid <= in_valid ;
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if( in_valid = '1' ) then
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interleaved <= interleave(modulation, data) ;
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interleaved_mod <= modulation ;
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end if ;
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end if ;
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end process ;
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end architecture ;
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