mirror of
https://github.com/Nuand/bladeRF-wiphy.git
synced 2024-12-19 05:38:09 +00:00
272 lines
9.5 KiB
VHDL
272 lines
9.5 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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library wlan ;
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use wlan.wlan_p.all ;
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use wlan.wlan_rx_p.all ;
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entity wlan_dsss_rx_framer is
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port (
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clock : in std_logic ;
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reset : in std_logic ;
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mode_bin : in natural ;
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demod_idx : in natural ;
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demod_bits : in std_logic_vector( 1 downto 0 ) ;
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demod_valid : in std_logic ;
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params : out wlan_rx_params_t ;
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params_valid : out std_logic ;
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data : out std_logic_vector( 7 downto 0 ) ;
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data_valid : out std_logic ;
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framer_done : out std_logic ;
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crc_correct : out std_logic
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) ;
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end entity ;
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architecture arch of wlan_dsss_rx_framer is
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type counter_t is array(0 to 19) of unsigned(4 downto 0) ;
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type fsm_t is (ACQUIRING, SEARCH_FOR_SFD, CAPTURE_PLCP, VERIFY_PLCP_CRC, CAPTURE_PAYLOAD, VERIFY_FCS, COMMIT_PKT) ;
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type state_t is record
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fsm : fsm_t ;
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mode_bin : natural range 0 to 20 ;
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sfd_attempt : natural range 0 to 120 ;
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byte_ready : std_logic ;
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byte_count : natural range 0 to 1200 ;
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pkt_len : natural range 0 to 1200 ;
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payload_len : natural range 0 to 1200 ;
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fcs : std_logic_vector( 31 downto 0 ) ;
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bit_count : natural range 0 to 60 ;
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recv_reg : std_logic_vector( 47 downto 0 ) ;
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consecutive_ones : counter_t ;
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plcp_crc_bit : std_logic ;
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plcp_crc_bit_valid : std_logic ;
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plcp_crc_init : std_logic ;
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params : wlan_rx_params_t ;
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params_valid : std_logic ;
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framer_done : std_logic ;
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crc_correct : std_logic ;
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end record ;
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function NULL_STATE return state_t is
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variable rv : state_t ;
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begin
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rv.fsm := ACQUIRING ;
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rv.mode_bin := 0 ;
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rv.sfd_attempt := 0 ;
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rv.byte_ready := '0' ;
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rv.byte_count := 0 ;
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rv.pkt_len := 0 ;
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rv.payload_len := 0 ;
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rv.fcs := ( others => '0' ) ;
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rv.bit_count := 0 ;
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rv.recv_reg := ( others => '0' ) ;
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rv.consecutive_ones := ( others => ( others => '0' ) ) ;
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rv.plcp_crc_bit := '0' ;
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rv.plcp_crc_bit_valid := '0' ;
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rv.plcp_crc_init := '0' ;
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rv.params_valid := '0' ;
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rv.params.packet_valid := '0' ;
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rv.framer_done := '0' ;
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return rv ;
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end function ;
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signal current, future : state_t := NULL_STATE ;
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signal plcp_crc : std_logic_vector( 15 downto 0 ) ;
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signal plcp_crc_endian : std_logic_vector( 15 downto 0 ) ;
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signal calculated_fcs : std_logic_vector( 31 downto 0 ) ;
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begin
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crc_correct <= current.crc_correct ;
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framer_done <= current.framer_done ;
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data <= current.recv_reg( 7 downto 0 ) ;
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data_valid <= current.byte_ready ;
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params_valid <= current.params_valid ;
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params <= current.params;
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U_plcp_crc : entity wlan.wlan_dsss_plcp_crc
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port map (
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clock => clock,
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reset => reset or current.plcp_crc_init,
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in_data => current.plcp_crc_bit,
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in_valid => current.plcp_crc_bit_valid,
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crc => plcp_crc
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) ;
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U_crc : entity wlan.wlan_crc
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port map (
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clock => clock,
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reset => reset or current.plcp_crc_init,
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in_data => current.recv_reg( 7 downto 0 ),
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in_valid => current.byte_ready,
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crc => calculated_fcs
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) ;
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sync : process(clock, reset)
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begin
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if( reset = '1' ) then
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current <= NULL_STATE ;
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elsif( rising_edge(clock) ) then
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current <= future ;
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end if ;
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end process ;
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comb : process( clock )
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begin
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for i in 0 to 7 loop
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plcp_crc_endian(i) <= plcp_crc(15 - i );
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plcp_crc_endian(8+i) <= plcp_crc(7 - i );
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end loop ;
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future <= current ;
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future.byte_ready <= '0' ;
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future.plcp_crc_bit_valid <= '0' ;
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future.plcp_crc_init <= '0' ;
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future.params_valid <= '0' ;
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future.params.packet_valid <= '0' ;
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future.framer_done <= '0' ;
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future.crc_correct <= '0' ;
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case current.fsm is
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when ACQUIRING =>
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if( demod_valid = '1' ) then
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if( demod_bits(0) = '1' ) then
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if(future.consecutive_ones(demod_idx) = 27 ) then
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future.consecutive_ones <= ( others => ( others => '0' ) ) ;
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future.mode_bin <= mode_bin ;
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future.sfd_attempt <= 0 ;
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future.plcp_crc_init <= '1' ;
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future.fsm <= SEARCH_FOR_SFD ;
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else
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future.consecutive_ones(demod_idx) <= current.consecutive_ones(demod_idx) + 1 ;
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end if ;
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else
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future.consecutive_ones(demod_idx) <= ( others => '0' ) ;
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end if ;
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end if ;
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when SEARCH_FOR_SFD =>
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if( demod_valid = '1' ) then
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if( demod_idx = current.mode_bin ) then
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future.recv_reg(15 downto 0) <= demod_bits(0) & current.recv_reg(15 downto 1) ;
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future.sfd_attempt <= current.sfd_attempt + 1 ;
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end if;
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end if;
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if( current.recv_reg(15 downto 0) = x"F3A0" ) then
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future.fsm <= CAPTURE_PLCP ;
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future.bit_count <= 1 ;
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elsif( current.sfd_attempt >= 130 ) then
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future.fsm <= ACQUIRING ;
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end if ;
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when CAPTURE_PLCP =>
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if( demod_valid = '1' and demod_idx = current.mode_bin ) then
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if( current.bit_count <= 32 ) then
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future.plcp_crc_bit <= demod_bits(0) ;
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future.plcp_crc_bit_valid <= '1' ;
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end if ;
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future.recv_reg <= demod_bits(0) & current.recv_reg(47 downto 1) ;
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if( current.bit_count = 48 ) then
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future.fsm <= VERIFY_PLCP_CRC ;
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end if ;
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future.bit_count <= current.bit_count + 1 ;
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end if ;
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when VERIFY_PLCP_CRC =>
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if( plcp_crc_endian = current.recv_reg(47 downto 32) ) then
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future.fsm <= CAPTURE_PAYLOAD ;
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future.byte_count <= 1 ;
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future.pkt_len <= to_integer(unsigned(current.recv_reg(31 downto 19))) ;
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future.payload_len <= to_integer(unsigned(current.recv_reg(31 downto 19))) - 4 ;
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future.bit_count <= 1 ;
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future.params_valid <= '1' ;
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future.params.datarate <= WLAN_RATE_1 ;
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future.params.length <= to_integer(unsigned(current.recv_reg(31 downto 19))) - 4 ;
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else
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future.fsm <= ACQUIRING ;
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end if ;
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future.recv_reg <= ( others => '0' ) ;
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when CAPTURE_PAYLOAD =>
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if( demod_valid = '1' and demod_idx = current.mode_bin ) then
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future.recv_reg(7 downto 0) <= demod_bits(0) & current.recv_reg(7 downto 1) ;
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if( current.bit_count = 8 ) then
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future.bit_count <= 1 ;
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if( current.byte_count > current.payload_len ) then
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future.fcs <= demod_bits(0) & current.recv_reg(7 downto 1) & current.fcs(31 downto 8) ;
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else
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future.byte_ready <= '1' ;
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end if ;
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if( current.byte_count = current.pkt_len ) then
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future.fsm <= VERIFY_FCS ;
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else
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future.byte_count <= current.byte_count + 1 ;
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end if ;
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else
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future.bit_count <= current.bit_count + 1 ;
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end if ;
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end if ;
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when VERIFY_FCS =>
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future.framer_done <= '1' ;
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if( current.fcs = calculated_fcs ) then
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future.crc_correct <= '1' ;
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future.fsm <= COMMIT_PKT ;
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else
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future.fsm <= ACQUIRING ;
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end if ;
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when COMMIT_PKT =>
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future.fsm <= ACQUIRING ;
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end case ;
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end process ;
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end architecture ;
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