mirror of
https://github.com/Nuand/bladeRF-wiphy.git
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119 lines
3.4 KiB
VHDL
119 lines
3.4 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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use ieee.math_real.all ;
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library work ;
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use work.wlan_p.all ;
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use work.wlan_tx_p.all ;
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entity wlan_tx_short is
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port (
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clock : in std_logic ;
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reset : in std_logic ;
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start : in std_logic ;
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done : out std_logic ;
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out_sample : out wlan_sample_t
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) ;
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end entity ;
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architecture arch of wlan_tx_short is
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function create_short_sequence return sample_array_t is
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variable rv : sample_array_t(SHORT_SEQ_TIME'range) ;
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begin
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for i in rv'range loop
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rv(i).i := to_signed(integer(round(SHORT_SEQ_TIME(i).re*4.0*4096.0)),rv(i).i'length) ;
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rv(i).q := to_signed(integer(round(SHORT_SEQ_TIME(i).im*4.0*4096.0)),rv(i).i'length) ;
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rv(i).valid := '1' ;
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end loop ;
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return rv ;
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end function ;
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constant SHORT_SEQ : sample_array_t := create_short_sequence ;
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type fsm_t is (IDLE, COUNTING) ;
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type state_t is record
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fsm : fsm_t ;
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repeat : natural range 1 to 10 ;
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index : natural range short_seq'range ;
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sample : wlan_sample_t ;
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done : std_logic ;
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end record ;
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constant NULL_STATE : state_t := (
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fsm => IDLE,
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repeat => 10,
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index => 0,
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sample => NULL_SAMPLE,
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done => '0'
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) ;
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-- FSM state
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signal current, future : state_t := NULL_STATE ;
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begin
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done <= current.done ;
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out_sample <= current.sample ;
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seq : process(clock, reset)
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begin
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if( reset = '1' ) then
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current <= NULL_STATE ;
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elsif( rising_edge(clock) ) then
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current <= future ;
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end if ;
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end process ;
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comb : process(all)
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begin
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future <= current ;
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case current.fsm is
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when IDLE =>
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future <= NULL_STATE ;
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if( start = '1' ) then
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future.fsm <= COUNTING ;
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end if ;
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when COUNTING =>
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future.sample <= short_seq(current.index) ;
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if( current.index < short_seq'high ) then
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future.index <= current.index + 1 ;
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else
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if( current.repeat = 1 ) then
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future.fsm <= IDLE ;
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future.done <= '1' ;
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else
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future.repeat <= current.repeat - 1 ;
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future.index <= 0 ;
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end if ;
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end if ;
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when others =>
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future <= NULL_STATE ;
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end case ;
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end process ;
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end architecture ;
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