mirror of
https://github.com/Nuand/bladeRF-wiphy.git
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126 lines
3.8 KiB
VHDL
126 lines
3.8 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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library work ;
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use work.wlan_p.all ;
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library altera_mf ;
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use altera_mf.altera_mf_components.all ;
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entity wlan_sample_buffer is
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port (
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clock : in std_logic ;
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reset : in std_logic ;
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-- Status
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room : out std_logic ;
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-- Short sequence inputs
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short : in wlan_sample_t ;
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-- Long sequence inputs
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long : in wlan_sample_t ;
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-- Symbol IFFT inputs
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symbol : in wlan_sample_t ;
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-- Sample FIFO outputs
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sample : out wlan_sample_t ;
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sample_i : out signed(15 downto 0) ;
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sample_q : out signed(15 downto 0) ;
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sample_re : in std_logic ;
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sample_empty : out std_logic
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) ;
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end entity ;
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architecture arch of wlan_sample_buffer is
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signal fifo_write : std_logic ;
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signal fifo_read : std_logic ;
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signal fifo_input : std_logic_vector(31 downto 0) ;
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signal fifo_output : std_logic_vector(31 downto 0) ;
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signal fifo_empty : std_logic ;
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signal fifo_full : std_logic ;
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signal fifo_usedw : std_logic_vector(9 downto 0) ;
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signal mux_i : signed(15 downto 0) ;
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signal mux_q : signed(15 downto 0) ;
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begin
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check_fifo : process(clock)
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begin
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if( rising_edge(clock) ) then
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if( fifo_full = '1' and fifo_write = '1' ) then
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report "Writing to a full FIFO"
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severity error ;
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end if ;
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end if ;
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end process ;
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fifo_input <= std_logic_vector(mux_i) & std_logic_vector(mux_q) ;
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fifo_write <= short.valid or long.valid or symbol.valid ;
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fifo_read <= sample_re ;
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sample_i <= signed(fifo_output(31 downto 16)) ;
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sample_q <= signed(fifo_output(15 downto 0)) ;
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sample_empty <= fifo_empty ;
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mux_input : process(all)
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begin
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if( short.valid = '1' ) then
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mux_i <= short.i ;
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mux_q <= short.q ;
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elsif( long.valid = '1' ) then
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mux_i <= long.i ;
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mux_q <= long.q ;
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elsif( symbol.valid = '1' ) then
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mux_i <= symbol.i ;
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mux_q <= symbol.q ;
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else
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mux_i <= (others =>'0') ;
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mux_q <= (others =>'0') ;
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end if ;
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end process ;
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room <= '1' when unsigned(fifo_usedw) < 2**(fifo_usedw'length)-128 else '0' ;
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U_fifo : scfifo
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generic map (
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lpm_width => fifo_input'length,
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lpm_widthu => fifo_usedw'length,
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lpm_numwords => 2**(fifo_usedw'length),
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lpm_showahead => "ON"
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) port map (
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clock => clock,
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aclr => reset,
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data => fifo_input,
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wrreq => fifo_write,
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rdreq => fifo_read,
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q => fifo_output,
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full => fifo_full,
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empty => fifo_empty,
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usedw => fifo_usedw
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) ;
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end architecture ;
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