mirror of
https://github.com/Nuand/bladeRF-wiphy.git
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817 lines
24 KiB
VHDL
817 lines
24 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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library wlan ;
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use wlan.nco_p.all ;
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use wlan.wlan_p.all ;
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use wlan.wlan_rx_p.all ;
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library altera_mf ;
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use altera_mf.altera_mf_components.all ;
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library wlan_pll ;
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entity wlan_rx is
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port (
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-- 40MHz clock and async asserted, sync deasserted reset
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clock40m : in std_logic ;
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reset40m : in std_logic ;
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-- Baseband input signals
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bb_i : in signed(15 downto 0) ;
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bb_q : in signed(15 downto 0) ;
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bb_valid : in std_logic ;
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equalized_i : out signed(15 downto 0) ;
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equalized_q : out signed(15 downto 0) ;
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equalized_valid : out std_logic ;
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-- AGC control signal
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gain_inc_req : out std_logic ;
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gain_dec_req : out std_logic ;
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gain_rst_req : out std_logic ;
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gain_ack : in std_logic ;
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gain_nack : in std_logic ;
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gain_lock : in std_logic ;
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gain_max : in std_logic ;
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-- ACK signals
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ack_mac : out std_logic_vector( 47 downto 0 ) ;
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ack_valid : out std_logic ;
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acked_packet : out std_logic ;
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rx_quiet : out std_logic ;
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rx_block : in std_logic ;
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-- RX status signals
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rx_end_of_packet: out std_logic ;
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rx_status : out wlan_rx_status_t ;
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rx_status_valid : out std_logic ;
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rx_vector : out wlan_rx_vector_t ;
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rx_vector_valid : out std_logic ;
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rx_data_req : in std_logic ;
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rx_data : out std_logic_vector( 7 downto 0 ) ;
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rx_data_valid : out std_logic ;
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mse : out unsigned(15 downto 0) ;
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mse_valid : out std_logic
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) ;
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end entity ;
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architecture arch of wlan_rx is
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signal rx_vector_rr : std_logic_vector( 3 downto 0 ) ;
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signal rx_vector_r : std_logic_vector( 3 downto 0 ) ;
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signal rx_end_of_packet_r : std_logic_vector( 3 downto 0 ) ;
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signal params : wlan_rx_params_t ;
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signal params_valid : std_logic ;
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signal bb_sample : wlan_sample_t ;
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signal bb_sample40 : wlan_sample_t ;
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signal sample : wlan_sample_t ;
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signal fft_sample : wlan_sample_t ;
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signal dfe_sample : wlan_sample_t ;
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signal eq_sample : wlan_sample_t ;
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signal phase_corr_sample : wlan_sample_t ;
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signal cfo_atan_average : signed( 31 downto 0 ) ;
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signal cfo_est_sample : wlan_sample_t ;
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signal p_mag : signed( 23 downto 0 ) ;
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signal acquired_packet : std_logic ;
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signal end_of_packet : std_logic ;
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signal acquired_sample : wlan_sample_t ;
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signal correction_dphase : signed( 15 downto 0 ) ;
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signal correction_dphase_valid : std_logic ;
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signal correction_p_mag : signed( 23 downto 0 ) ;
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signal correction_p_mag_valid : std_logic ;
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signal symbol_start : std_logic ;
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signal fft_done : std_logic ;
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signal eq_done : std_logic ;
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signal phase_corr_done : std_logic ;
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signal demod_modulation : wlan_modulation_t ;
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signal demod_data : std_logic_vector( 287 downto 0 ) ;
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signal demod_bsds : bsd_array_t(287 downto 0) ;
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signal demod_valid : std_logic ;
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signal deinter_modulation : wlan_modulation_t ;
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signal deinter_data : std_logic_vector( 287 downto 0 ) ;
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signal deinter_bsds : bsd_array_t(287 downto 0) ;
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signal deinter_valid : std_logic ;
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signal depunct_done : std_logic ;
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signal depunct_empty : std_logic ;
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signal depunct_soft_a : signed( 7 downto 0 ) ;
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signal depunct_soft_b : signed( 7 downto 0 ) ;
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signal depunct_erasure : std_logic_vector( 1 downto 0 ) ;
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signal depunct_valid : std_logic ;
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signal num_decoded_bits : unsigned( 13 downto 0 ) ;
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signal num_decoded_bits_valid : std_logic ;
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signal decoder_done : std_logic ;
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signal rx_packet_init : std_logic ;
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signal decoded_bit : std_logic;
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signal decoded_valid : std_logic;
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signal descrambled_data : std_logic_vector( 7 downto 0 ) ;
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signal descrambled_valid : std_logic ;
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signal descrambler_bypass : std_logic ;
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signal signal_dec : std_logic ;
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signal rx_framer_done : std_logic ;
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-- Block Diagram of the modem
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-- acquisition -> cfo est/removal -> equalizer -> demod -> depuncture -> fec -> framer
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-- ^-----------------------------------------'
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--
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-- The equalizer can't move onward until there is the feedback from
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-- the framer to understand the SIGNAL field, so FFT frames are buffered
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-- until the actual payload size and length is known and at least seems
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-- plausible.
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signal clock : std_logic ;
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signal bb_valid_80m : std_logic ;
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signal bb_valid_r : std_logic ;
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signal rst_gains : std_logic ;
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signal burst : std_logic ;
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signal framer_quiet_reset : std_logic ;
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signal rx_data_rdempty : std_logic ;
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signal crc_correct : std_logic ;
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signal ack_valid_r : std_logic ;
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signal ack_valid_rr80 : std_logic_vector( 3 downto 0 ) ;
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signal ack_valid_rr : std_logic_vector( 3 downto 0 ) ;
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signal acked_packet_r : std_logic ;
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signal acked_packet_rr80 : std_logic_vector( 3 downto 0 ) ;
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signal acked_packet_rr : std_logic_vector( 3 downto 0 ) ;
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signal buf_params : wlan_rx_params_t ;
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signal buf_params_valid : std_logic ;
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signal buf_data : std_logic_vector( 7 downto 0 ) ;
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signal buf_data_valid : std_logic ;
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signal buf_end_of_packet : std_logic ;
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signal dsss_params : wlan_rx_params_t ;
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signal dsss_params_valid : std_logic ;
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signal dsss_data : std_logic_vector( 7 downto 0 ) ;
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signal dsss_data_valid : std_logic ;
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signal dsss_framer_done : std_logic ;
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signal dsss_crc_correct : std_logic ;
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signal dsss_params_80m : wlan_rx_params_t ;
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signal dsss_params_valid_80m : std_logic ;
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signal dsss_data_80m : std_logic_vector( 7 downto 0 ) ;
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signal dsss_data_valid_80m : std_logic ;
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signal dsss_framer_done_80m : std_logic ;
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signal dsss_crc_correct_80m : std_logic ;
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component wlan_pll
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port (
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refclk : in std_logic;
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rst : in std_logic;
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outclk_0 : out std_logic;
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locked : out std_logic
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);
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end component;
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signal r_bb_i : signed(15 downto 0) ;
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signal r_bb_q : signed(15 downto 0) ;
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signal r_bb_valid : std_logic ;
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signal wfull : std_logic ;
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signal rempty : std_logic ;
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signal fvalid : std_logic ;
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signal fdata : std_logic_vector(31 downto 0) ;
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signal f_bb_i : signed(15 downto 0) ;
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signal f_bb_q : signed(15 downto 0) ;
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signal rst_rr : std_logic_vector(2 downto 0);
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signal reset : std_logic ;
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begin
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rx_quiet <= not burst ;
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equalized_i <= phase_corr_sample.i( 15 downto 0 ) ;
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equalized_q <= phase_corr_sample.q( 15 downto 0 ) ;
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equalized_valid <= phase_corr_sample.valid;
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process(all)
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begin
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if( rising_edge( clock ) ) then
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rst_rr <= reset40m & rst_rr(rst_rr'high downto 1);
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end if;
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end process;
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reset <= rst_rr(0);
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U_rx_data_dc_fifo: dcfifo
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generic map (
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lpm_width => 32,
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lpm_widthu => 5,
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lpm_numwords => 32,
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lpm_showahead => "ON"
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)
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port map (
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aclr => reset,
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wrclk => clock40m,
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wrreq => bb_valid and not wfull,
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data => std_logic_vector(bb_i) & std_logic_vector(bb_q),
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wrfull => wfull,
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wrempty => open,
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wrusedw => open,
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rdclk => clock,
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rdreq => fvalid,
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q => fdata,
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rdfull => open,
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rdempty => rempty,
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rdusedw => open
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) ;
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fvalid <= not rempty;
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f_bb_i <= signed(fdata(31 downto 16));
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f_bb_q <= signed(fdata(15 downto 0));
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process(clock40m, reset)
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begin
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if( reset = '1' ) then
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r_bb_i <= ( others => '0' ) ;
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r_bb_q <= ( others => '0' ) ;
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r_bb_valid <= '0';
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elsif( rising_edge( clock40m ) ) then
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r_bb_i <= bb_i ;
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r_bb_q <= bb_q ;
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r_bb_valid <= bb_valid ;
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end if;
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end process;
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process(clock, reset)
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begin
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if( reset = '1' ) then
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bb_valid_r <= '0' ;
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bb_valid_80m <= '0' ;
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elsif( rising_edge( clock ) ) then
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bb_valid_r <= r_bb_valid ;
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if( r_bb_valid = '1' and bb_valid_r = '0' ) then
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bb_valid_80m <= '1' ;
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else
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bb_valid_80m <= '0' ;
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end if ;
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end if ;
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end process ;
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U_80mhz_clock: component wlan_pll
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port map (
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refclk => clock40m,
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rst => '0',
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outclk_0 => clock,
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locked => open
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);
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-- Input sample assignment
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bb_sample.i <= f_bb_i;
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bb_sample.q <= f_bb_q;
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bb_sample.valid <= fvalid;
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bb_sample40.i <= r_bb_i;
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bb_sample40.q <= r_bb_q;
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bb_sample40.valid <= r_bb_valid;
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U_agc : entity work.wlan_agc
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port map (
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clock => clock40m,
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reset => reset40m,
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agc_hold_req => '0',
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gain_inc_req => gain_inc_req,
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gain_dec_req => gain_dec_req,
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gain_rst_req => gain_rst_req,
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gain_ack => gain_ack,
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gain_nack => gain_nack,
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gain_max => gain_max,
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rst_gains => rst_gains,
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burst => burst,
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sample_i => bb_i,
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sample_q => bb_q,
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sample_valid => bb_valid
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) ;
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U_csma : entity wlan.wlan_csma
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port map (
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clock => clock,
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reset => reset,
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in_sample => acquired_sample,
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quiet => open
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) ;
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U_dsss : entity wlan.wlan_dsss_rx
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port map (
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clock => clock40m,
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reset => reset40m,
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sample => bb_sample40,
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params => dsss_params,
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params_valid => dsss_params_valid,
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data => dsss_data,
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data_valid => dsss_data_valid,
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framer_done => dsss_framer_done,
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crc_correct => dsss_crc_correct
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) ;
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U_dsss_sync_params : entity wlan.clock_sync_params
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port map (
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from_signal => dsss_params,
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to_clock => clock,
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to_reset => reset,
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to_signal => dsss_params_80m
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) ;
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U_dsss_sync_params_valid : entity wlan.clock_sync_logic
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port map (
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from_signal => dsss_params_valid,
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to_clock => clock,
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to_reset => reset,
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to_signal => dsss_params_valid_80m
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) ;
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U_dsss_sync_data : entity wlan.clock_sync_logic_vector
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port map (
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from_signal => dsss_data,
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to_clock => clock,
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to_reset => reset,
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to_signal => dsss_data_80m
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) ;
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U_dsss_sync_data_valid : entity wlan.clock_sync_logic
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port map (
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from_signal => dsss_data_valid,
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to_clock => clock,
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to_reset => reset,
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to_signal => dsss_data_valid_80m
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) ;
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U_dsss_sync_framer_done : entity wlan.clock_sync_logic
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port map (
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from_signal => dsss_framer_done,
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to_clock => clock,
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to_reset => reset,
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to_signal => dsss_framer_done_80m
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) ;
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U_dsss_sync_crc_correct : entity wlan.clock_sync_logic
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port map (
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from_signal => dsss_crc_correct,
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to_clock => clock,
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to_reset => reset,
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to_signal => dsss_crc_correct_80m
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) ;
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U_acquisition : entity wlan.wlan_acquisition
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port map (
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clock => clock40m,
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reset => reset40m,
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acquired => acquired_packet,
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p_mag => p_mag,
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in_sample => bb_sample40,
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quiet => not burst or gain_lock,
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burst => burst,
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out_sample => acquired_sample
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);
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U_cfo : entity wlan.wlan_cfo_estimate
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port map (
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clock => clock40m,
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reset => reset40m,
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in_sample => acquired_sample,
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out_sample => cfo_est_sample,
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atan_average => cfo_atan_average
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) ;
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U_cfo_correction : entity wlan.wlan_cfo_correction
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port map (
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clock => clock,
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reset => reset,
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dphase => correction_dphase,
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dphase_valid => '0',
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p_mag => correction_p_mag,
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p_mag_valid => correction_p_mag_valid,
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in_sample => bb_sample,
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out_sample => sample
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) ;
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U_rx_controller : entity wlan.wlan_rx_controller
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port map (
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clock => clock,
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reset => reset,
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framer_quiet_reset => framer_quiet_reset,
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params => params,
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params_valid => params_valid,
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rx_packet_init => rx_packet_init,
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rx_quiet => not burst,
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rx_framer_done => rx_framer_done,
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sample_valid => sample.valid,
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end_of_packet => end_of_packet,
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-- acquistion
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acquired => acquired_packet and not rx_block,
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p_mag => p_mag,
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-- CFO estimation
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atan_average => resize( cfo_atan_average, 16 ),
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-- CFO correction
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c_dphase => correction_dphase,
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c_dphase_valid => correction_dphase_valid,
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c_p_mag => correction_p_mag,
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c_p_mag_valid => correction_p_mag_valid,
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-- FFT
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symbol_start => symbol_start
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) ;
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U_fft: entity wlan.wlan_fft64
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port map (
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clock => clock,
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reset => reset,
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init => rx_packet_init,
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signal_dec => signal_dec,
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dphase => correction_dphase,
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symbol_start => symbol_start,
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in_sample => sample,
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out_sample => fft_sample,
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done => fft_done
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) ;
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-- Insert buffer here?
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-- Equalizer need to know what modulation it's equalizin
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U_eq: entity wlan.wlan_equalizer
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port map (
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clock => clock,
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reset => reset,
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init => rx_packet_init,
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dfe_sample => dfe_sample,
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in_sample => fft_sample,
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in_done => fft_done,
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out_sample => eq_sample,
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out_done => eq_done
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) ;
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U_phase_correct: entity wlan.wlan_phase_correction
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port map (
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clock => clock,
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reset => reset,
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init => rx_packet_init,
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in_sample => eq_sample,
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in_done => eq_done,
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out_sample => phase_corr_sample,
|
|
out_done => phase_corr_done
|
|
) ;
|
|
|
|
U_demod: entity wlan.wlan_demodulator
|
|
port map (
|
|
clock => clock,
|
|
reset => reset,
|
|
|
|
init => rx_packet_init,
|
|
|
|
params => params,
|
|
params_valid => params_valid,
|
|
|
|
in_sample => phase_corr_sample,
|
|
in_done => phase_corr_done,
|
|
|
|
dfe_sample => dfe_sample,
|
|
|
|
out_mod => demod_modulation,
|
|
-- FIXME: Change to output BSDs
|
|
out_data => demod_bsds,
|
|
out_valid => demod_valid
|
|
) ;
|
|
|
|
U_deinterleaver: entity wlan.wlan_deinterleaver
|
|
port map (
|
|
clock => clock,
|
|
reset => reset,
|
|
|
|
modulation => demod_modulation,
|
|
data => demod_bsds,
|
|
in_valid => demod_valid,
|
|
|
|
depuncturer_empty => depunct_empty,
|
|
|
|
deinterleaved_mod => deinter_modulation,
|
|
deinterleaved => deinter_bsds,
|
|
deinterleaved_valid => deinter_valid
|
|
) ;
|
|
|
|
U_depunct : entity wlan.wlan_depuncturer
|
|
port map (
|
|
clock => clock,
|
|
reset => reset,
|
|
|
|
init => rx_packet_init,
|
|
|
|
modulation => deinter_modulation,
|
|
data => deinter_bsds,
|
|
in_valid => deinter_valid,
|
|
|
|
params => params,
|
|
params_valid => params_valid,
|
|
|
|
end_zero_pad => decoder_done,
|
|
empty => depunct_empty,
|
|
|
|
out_soft_a => depunct_soft_a,
|
|
out_soft_b => depunct_soft_b,
|
|
out_erasure => depunct_erasure,
|
|
out_valid => depunct_valid
|
|
) ;
|
|
|
|
U_decoder : entity wlan.wlan_viterbi_decoder
|
|
port map (
|
|
clock => clock,
|
|
reset => reset,
|
|
|
|
init => rx_packet_init,
|
|
|
|
in_soft_a => depunct_soft_a,
|
|
in_soft_b => depunct_soft_b,
|
|
in_erasure => depunct_erasure,
|
|
in_valid => depunct_valid,
|
|
|
|
params => params,
|
|
params_valid => params_valid,
|
|
|
|
done => decoder_done,
|
|
|
|
out_dec_bit => decoded_bit,
|
|
out_dec_valid => decoded_valid
|
|
) ;
|
|
|
|
U_descrambler : entity wlan.wlan_descrambler
|
|
port map (
|
|
clock => clock,
|
|
reset => reset,
|
|
|
|
init => rx_packet_init,
|
|
|
|
params => params,
|
|
params_valid => params_valid,
|
|
|
|
bypass => descrambler_bypass,
|
|
|
|
in_data => decoded_bit,
|
|
in_valid => decoded_valid,
|
|
|
|
out_data => descrambled_data,
|
|
out_valid => descrambled_valid,
|
|
out_done => open
|
|
) ;
|
|
|
|
U_rx_sample_fifo: dcfifo
|
|
generic map (
|
|
lpm_width => 8,
|
|
lpm_widthu => 11,
|
|
lpm_numwords => 1600,
|
|
lpm_showahead => "ON"
|
|
)
|
|
port map (
|
|
aclr => reset,
|
|
|
|
wrclk => clock,
|
|
wrreq => buf_data_valid,
|
|
data => buf_data,
|
|
|
|
wrfull => open,
|
|
wrempty => open,
|
|
wrusedw => open,
|
|
|
|
rdclk => clock40m,
|
|
rdreq => (not rx_data_rdempty) and rx_data_req,
|
|
q => rx_data,
|
|
|
|
rdfull => open,
|
|
rdempty => rx_data_rdempty,
|
|
rdusedw => open
|
|
) ;
|
|
rx_data_valid <= (not rx_data_rdempty) and rx_data_req ;
|
|
|
|
rx_vector.length <= buf_params.length;
|
|
rx_vector.datarate <= buf_params.datarate;
|
|
rx_vector.bandwidth <= buf_params.bandwidth;
|
|
rx_vector_valid <= rx_vector_rr(0) ;
|
|
rx_end_of_packet <= rx_data_rdempty ;
|
|
|
|
process(all)
|
|
begin
|
|
if( reset = '1' ) then
|
|
rx_vector_r <= ( others => '0' ) ;
|
|
rx_end_of_packet_r <= ( others => '0' ) ;
|
|
elsif( rising_edge( clock ) ) then
|
|
if( buf_params_valid = '1' ) then
|
|
rx_vector_r <= ( others => '1' ) ;
|
|
else
|
|
rx_vector_r <= '0' & rx_vector_r(3 downto 1) ;
|
|
end if ;
|
|
|
|
if( buf_end_of_packet = '1' ) then
|
|
rx_end_of_packet_r <= ( others => '1' ) ;
|
|
else
|
|
rx_end_of_packet_r <= '0' & rx_end_of_packet_r(3 downto 1) ;
|
|
end if ;
|
|
end if ;
|
|
end process ;
|
|
|
|
process(all)
|
|
begin
|
|
if( reset = '1' ) then
|
|
rx_vector_rr <= ( others => '0' ) ;
|
|
acked_packet_rr <= ( others => '0' ) ;
|
|
elsif( rising_edge( clock40m ) ) then
|
|
rx_vector_rr <= rx_vector_r(0) & rx_vector_rr(3 downto 1) ;
|
|
|
|
ack_valid_rr <= ack_valid_rr80(0) & ack_valid_rr(3 downto 1) ;
|
|
if( ack_valid_rr(1 downto 0) = "10" ) then
|
|
ack_valid <= '1' ;
|
|
else
|
|
ack_valid <= '0' ;
|
|
end if ;
|
|
|
|
acked_packet_rr <= acked_packet_rr80(0) & acked_packet_rr(3 downto 1) ;
|
|
if( acked_packet_rr(1 downto 0) = "10" ) then
|
|
acked_packet <= '1' ;
|
|
else
|
|
acked_packet <= '0' ;
|
|
end if ;
|
|
end if ;
|
|
end process ;
|
|
|
|
process(all)
|
|
begin
|
|
if( reset = '1' ) then
|
|
ack_valid_rr80 <= ( others => '0' ) ;
|
|
acked_packet_rr80 <= (others => '0' ) ;
|
|
elsif( rising_edge( clock ) ) then
|
|
if( ack_valid_r = '1' ) then
|
|
ack_valid_rr80 <= ( others => '1' ) ;
|
|
else
|
|
ack_valid_rr80 <= '0' & ack_valid_rr80( 3 downto 1 ) ;
|
|
end if ;
|
|
if( acked_packet_r = '1' ) then
|
|
acked_packet_rr80 <= ( others => '1' ) ;
|
|
else
|
|
acked_packet_rr80 <= '0' & acked_packet_rr80( 3 downto 1 ) ;
|
|
end if ;
|
|
end if ;
|
|
end process ;
|
|
|
|
|
|
|
|
U_framer : entity wlan.wlan_rx_framer
|
|
port map (
|
|
clock => clock,
|
|
reset => reset,
|
|
|
|
framer_quiet_reset => framer_quiet_reset,
|
|
init => rx_packet_init,
|
|
|
|
bss_mac => x"70B3D57D8001",
|
|
|
|
ack_mac => ack_mac,
|
|
ack_valid => ack_valid_r,
|
|
|
|
acked_packet => acked_packet_r,
|
|
|
|
params => params,
|
|
params_valid => params_valid,
|
|
|
|
in_data => descrambled_data,
|
|
in_valid => descrambled_valid,
|
|
|
|
signal_dec => signal_dec,
|
|
|
|
descrambler_bypass => descrambler_bypass,
|
|
|
|
crc_correct => crc_correct,
|
|
|
|
depunct_done => depunct_done,
|
|
|
|
decoder_done => decoder_done,
|
|
|
|
framer_done => rx_framer_done
|
|
) ;
|
|
|
|
U_rx_packet_buffer : entity wlan.wlan_rx_packet_buffer
|
|
port map (
|
|
clock => clock,
|
|
reset => reset,
|
|
|
|
framer_quiet_reset => framer_quiet_reset,
|
|
framer_done => rx_framer_done,
|
|
crc_correct => crc_correct,
|
|
|
|
in_params => params,
|
|
in_params_valid => params_valid and signal_dec,
|
|
|
|
in_data => descrambled_data,
|
|
in_data_valid => descrambled_valid and signal_dec,
|
|
|
|
dsss_params => dsss_params_80m,
|
|
dsss_params_valid => dsss_params_valid_80m,
|
|
|
|
dsss_data => dsss_data_80m,
|
|
dsss_data_valid => dsss_data_valid_80m,
|
|
|
|
dsss_framer_done => dsss_framer_done_80m,
|
|
dsss_crc_correct => dsss_crc_correct_80m,
|
|
|
|
out_params => buf_params,
|
|
out_params_valid => buf_params_valid,
|
|
|
|
out_data => buf_data,
|
|
out_data_valid => buf_data_valid,
|
|
|
|
out_end_of_packet => buf_end_of_packet
|
|
) ;
|
|
|
|
end architecture ;
|
|
|