mirror of
https://github.com/Nuand/bladeRF-wiphy.git
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335 lines
12 KiB
VHDL
335 lines
12 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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library wlan ;
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library work ;
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use work.wlan_p.all ;
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use work.wlan_tx_p.all ;
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entity wlan_framer is
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port (
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clock : in std_logic ;
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reset : in std_logic ;
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params : in wlan_tx_params_t ;
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params_valid : in std_logic ;
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encoder_start : in std_logic ;
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fifo_data : in std_logic_vector(7 downto 0) ;
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fifo_empty : in std_logic ;
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fifo_re : out std_logic ;
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buffer_room : in std_logic ;
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mod_done : in std_logic ;
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out_data : out std_logic_vector(7 downto 0) ;
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out_valid : out std_logic ;
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done : out std_logic
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) ;
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end entity ;
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architecture arch of wlan_framer is
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type fsm_t is (IDLE, FRAME_SIGNAL, WAIT_FOR_SIGNAL_MODULATED, FRAME_SERVICE, FRAME_DATA, WAIT_ZZ, WAIT_YY, WAIT_FOR_DATA_MODULATED, WAIT_FOR_BUFFER_ROOM) ;
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type signal_field_t is record
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rate : unsigned(3 downto 0) ;
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length : unsigned(11 downto 0) ;
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parity : std_logic ;
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end record ;
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function "xor"(x : std_logic_vector) return std_logic is
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variable rv : std_logic := '0' ;
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begin
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for i in x'range loop
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rv := x(i) xor rv ;
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end loop ;
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return rv ;
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end function ;
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function calculate_parity( x : signal_field_t ) return std_logic is
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constant xx : std_logic_vector(15 downto 0) := std_logic_vector(x.rate & x.length) ;
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constant rv : std_logic := "xor"(xx) ;
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begin
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return rv ;
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end function ;
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type state_t is record
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fsm : fsm_t ;
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signal_field : signal_field_t ;
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signal_slv : unsigned(23 downto 0) ;
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done : std_logic ;
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bytes_left : natural range 0 to 4095 ;
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symbol_bytes_left : natural range 0 to 27 ;
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puncturing_nibble : std_logic ;
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extra_byte : std_logic ;
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symbol_bytes : natural range 0 to 27 ;
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data : std_logic_vector(7 downto 0) ;
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crc_data_valid : std_logic ;
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data_valid : std_logic ;
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fifo_re : std_logic ;
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crc_reset : std_logic ;
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crc_mux : std_logic ;
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crc_index : natural range 0 to 8 ;
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bad_index : natural range 0 to 80 ;
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end record ;
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function NULL_STATE return state_t is
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variable rv : state_t ;
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begin
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rv.fsm := IDLE ;
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rv.signal_field := ( (others =>'0'), (others =>'0'), '0' ) ;
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rv.signal_slv := (others =>'0') ;
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rv.done := '0' ;
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rv.bytes_left := 0 ;
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rv.puncturing_nibble := '0' ;
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rv.extra_byte := '0' ;
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rv.symbol_bytes := 0 ;
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rv.symbol_bytes_left := 0 ;
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rv.data := (others =>'0') ;
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rv.crc_data_valid := '0' ;
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rv.data_valid := '0' ;
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rv.fifo_re := '0' ;
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rv.crc_reset := '0' ;
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rv.crc_mux := '0' ;
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rv.crc_index := 0 ;
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rv.bad_index := 0 ;
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return rv ;
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end function ;
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function pack( x : signal_field_t ) return unsigned is
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variable rv : unsigned(23 downto 0) ;
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begin
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rv(3 downto 0) := x.rate ;
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rv(4) := '0' ;
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rv(16 downto 5) := x.length ;
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rv(17) := x.parity ;
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rv(23 downto 18) := (others =>'0') ;
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return rv ;
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end function ;
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signal current, future : state_t := NULL_STATE ;
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signal calculated_crc : std_logic_vector( 31 downto 0 ) ;
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begin
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fifo_re <= current.fifo_re ;
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out_valid <= current.data_valid ;
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done <= current.done ;
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process(all)
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begin
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if( current.crc_mux = '1' ) then
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case current.crc_index is
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when 0 => out_data <= calculated_crc( 31 downto 24 ) ;
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when 1 => out_data <= calculated_crc( 23 downto 16 ) ;
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when 2 => out_data <= calculated_crc( 15 downto 8 ) ;
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when 3 => out_data <= calculated_crc( 7 downto 0 ) ;
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when others => out_data <= ( others => '0' ) ;
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end case ;
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else
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out_data <= current.data ;
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end if ;
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end process ;
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sync : process(clock, reset)
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begin
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if( reset = '1' ) then
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current <= NULL_STATE ;
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elsif( rising_edge(clock) ) then
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current <= future ;
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end if ;
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end process ;
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comb : process(all)
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variable sf : signal_field_t ;
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begin
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sf := ( (others =>'0'), (others =>'0'), '0' ) ;
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future <= current ;
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future.done <= '0' ;
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future.crc_data_valid <= '0' ;
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future.data_valid <= '0' ;
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future.fifo_re <= '0' ;
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future.crc_reset <= '0' ;
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case current.fsm is
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when IDLE =>
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future.crc_mux <= '0' ;
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if( encoder_start = '1' ) then
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future.fsm <= FRAME_SIGNAL ;
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sf.length := to_unsigned( params.length, sf.length'length ) + 4 ;
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case params.datarate is
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-- Note table goes R4-R1 instead of R1-R4
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when WLAN_RATE_6 => sf.rate := "1011" ;
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when WLAN_RATE_9 => sf.rate := "1111" ;
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when WLAN_RATE_12 => sf.rate := "1010" ;
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when WLAN_RATE_18 => sf.rate := "1110" ;
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when WLAN_RATE_24 => sf.rate := "1001" ;
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when WLAN_RATE_36 => sf.rate := "1101" ;
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when WLAN_RATE_48 => sf.rate := "1000" ;
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when WLAN_RATE_54 => sf.rate := "1100" ;
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when others => report "Error in datarate" severity failure ;
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end case ;
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sf.parity := calculate_parity( sf ) ;
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future.signal_field <= sf ;
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future.signal_slv <= pack(sf) ;
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future.bytes_left <= 3-1 ;
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future.symbol_bytes <= params.n_dbps/8 ;
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future.symbol_bytes_left <= params.n_dbps/8 - 1;
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future.crc_reset <= '1' ;
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if( params.datarate = WLAN_RATE_9) then
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future.puncturing_nibble <= '1' ;
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future.extra_byte <= '1' ;
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else
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future.puncturing_nibble <= '0' ;
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end if ;
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end if ;
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when FRAME_SIGNAL =>
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-- SIGNAL field needs to be packed and sent out unscrambled
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future.data <= std_logic_vector(current.signal_slv(7 downto 0)) ;
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future.data_valid <= '1' ;
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if( current.bytes_left = 0 ) then
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future.fsm <= WAIT_FOR_SIGNAL_MODULATED ;
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future.bytes_left <= 2-1 ;
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else
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future.signal_slv <= shift_right(current.signal_slv,8) ;
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future.bytes_left <= current.bytes_left - 1 ;
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end if ;
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when WAIT_FOR_SIGNAL_MODULATED =>
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if( mod_done = '1' ) then
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future.fsm <= FRAME_SERVICE ;
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future.bad_index <= 0;
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end if ;
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when WAIT_ZZ =>
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if( current.bad_index = 70 ) then
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future.fsm <= FRAME_SERVICE ;
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else
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future.bad_index <= current.bad_index + 1;
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end if;
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when FRAME_SERVICE =>
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future.data <= (others =>'0') ;
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future.data_valid <= '1' ;
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if( current.bytes_left = 0 ) then
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future.fifo_re <= '1' ;
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future.fsm <= FRAME_DATA ;
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future.bytes_left <= to_integer(current.signal_field.length) - 1 ;
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if( current.puncturing_nibble = '1' and current.extra_byte = '1' ) then
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future.symbol_bytes_left <= current.symbol_bytes - 2 ;
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future.extra_byte <= '0' ;
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else
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future.symbol_bytes_left <= current.symbol_bytes - 2 - 1 ;
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end if ;
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else
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future.bytes_left <= current.bytes_left - 1 ;
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end if ;
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when FRAME_DATA =>
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future.data_valid <= '1' ;
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if( current.bytes_left = 3 ) then
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future.crc_index <= 3 ;
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elsif( current.bytes_left < 3 ) then
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future.crc_index <= current.crc_index - 1 ;
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end if ;
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if( current.bytes_left <= 3 ) then
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future.crc_mux <= '1' ;
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else
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future.data <= fifo_data ;
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future.crc_data_valid <= '1' ;
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if( current.bytes_left > 4 ) then
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future.fifo_re <= '1' ;
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end if;
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end if ;
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if( current.bytes_left = 0 ) then
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future.fsm <= IDLE ;
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future.done <= '1' ;
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else
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if( current.symbol_bytes_left = 0 ) then
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future.fifo_re <= '0' ;
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future.fsm <= WAIT_FOR_DATA_MODULATED ;
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else
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future.symbol_bytes_left <= current.symbol_bytes_left - 1 ;
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end if ;
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future.bytes_left <= current.bytes_left - 1 ;
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end if ;
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when WAIT_FOR_DATA_MODULATED =>
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if( mod_done = '1' ) then
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if( current.puncturing_nibble = '1' ) then
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if( current.extra_byte = '1' ) then
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future.symbol_bytes_left <= current.symbol_bytes ;
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else
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future.symbol_bytes_left <= current.symbol_bytes - 1 ;
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end if;
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future.extra_byte <= not current.extra_byte ;
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else
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future.symbol_bytes_left <= current.symbol_bytes - 1 ;
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end if;
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if( buffer_room = '1' ) then
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future.bad_index <= 0;
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future.fsm <= FRAME_DATA ;
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future.fifo_re <= '1' ;
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else
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future.fsm <= WAIT_FOR_BUFFER_ROOM ;
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end if ;
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end if ;
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when WAIT_YY =>
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if( current.bad_index = 32 ) then
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future.fsm <= FRAME_DATA ;
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future.fifo_re <= '1' ;
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else
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future.bad_index <= current.bad_index + 1;
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end if;
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when WAIT_FOR_BUFFER_ROOM =>
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if( buffer_room = '1' ) then
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future.fifo_re <= '1' ;
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future.fsm <= FRAME_DATA ;
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end if ;
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when others =>
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future.fsm <= IDLE ;
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end case ;
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end process ;
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U_crc : entity wlan.wlan_crc
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port map (
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clock => clock,
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reset => reset or current.crc_reset,
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in_data => current.data,
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in_valid => current.crc_data_valid,
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crc => calculated_crc
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) ;
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end architecture ;
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