mirror of
https://github.com/Nuand/bladeRF-wiphy.git
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115 lines
3.3 KiB
VHDL
115 lines
3.3 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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use ieee.math_real.all ;
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library wlan ;
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use wlan.wlan_p.all ;
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use wlan.wlan_rx_p.all ;
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library wlan;
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entity wlan_acquisition_tb is
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end entity ;
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architecture arch of wlan_acquisition_tb is
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signal clock : std_logic := '0' ;
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signal sample : wlan_sample_t ;
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signal fopen : std_logic;
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signal reset : std_logic;
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signal i_sum : signed(63 downto 0);
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signal q_sum : signed(63 downto 0);
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signal sum : signed(127 downto 0);
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signal acquired_packet : std_logic ;
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signal p_mag : signed(23 downto 0) ;
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type SAMPLE_ARRAY is array (integer range <>) of wlan_sample_t;
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signal samples : SAMPLE_ARRAY(0 to 159);
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begin
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clock <= not clock after 10 ns;
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reset <= '1', '0' after 50 ns ;
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fopen <= '0', '1' after 100 ns;
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U_sample_loader: entity wlan.wlan_sample_loader
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generic map (
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FILENAME => "tx"
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) port map (
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clock => clock,
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fopen => fopen,
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sample => sample
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);
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U_csma : entity wlan.wlan_csma
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port map (
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clock => clock,
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reset => reset,
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in_sample => sample,
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quiet => open
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) ;
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U_acquisition : entity wlan.wlan_acquisition
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port map (
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clock => clock,
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reset => reset,
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in_sample => sample,
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acquired => acquired_packet,
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p_mag => p_mag,
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quiet => '0',
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burst => '0',
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out_sample => open
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);
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tb : process(clock)
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variable tsum : signed(127 downto 0);
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variable isum : signed(63 downto 0);
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variable qsum : signed(63 downto 0);
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begin
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if( rising_edge( clock ) ) then
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if( sample.valid = '1' ) then
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for i in 0 to samples'high - 1 loop
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samples(i+1) <= samples(i);
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end loop ;
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samples(0) <= sample;
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isum := (others => '0');
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qsum := (others => '0');
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for i in 0 to 79 loop
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isum := isum + samples(i).i * samples(i + 80).i + samples(i).q * samples(i + 80).q;
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qsum := qsum - samples(i).i * samples(i + 80).q + samples(i).q * samples(i + 80).i;
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end loop ;
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i_sum <= isum;
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q_sum <= qsum;
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tsum := isum * isum + qsum * qsum;
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sum <= tsum;
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end if;
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end if ;
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end process ;
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end architecture ;
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