mirror of
https://github.com/Nuand/bladeRF-wiphy.git
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135 lines
4.8 KiB
VHDL
135 lines
4.8 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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library wlan ;
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use wlan.wlan_p.all ;
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use wlan.wlan_rx_p.all ;
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entity wlan_csma is
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port (
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clock : in std_logic ;
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reset : in std_logic ;
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in_sample : in wlan_sample_t ;
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quiet : out std_logic
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) ;
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end entity ;
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architecture arch of wlan_csma is
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type fsm_t is (IDLE, CAPTURE_PHY_NOISE, CSMA) ;
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type unsigned_array_t is array (natural range 0 to 79) of unsigned( 31 downto 0 ) ;
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type state_t is record
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fsm : fsm_t ;
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quiet : std_logic ;
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timer : unsigned( 23 downto 0 ) ;
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powersum : unsigned( 31 downto 0 ) ;
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min_phy_noise : unsigned( 31 downto 0 ) ;
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history : unsigned_array_t ;
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end record ;
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function NULL_STATE return state_t is
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variable rv : state_t ;
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begin
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rv.fsm := IDLE ;
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rv.timer := ( others => '0' ) ;
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rv.min_phy_noise := ( others => '1' ) ;
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rv.powersum := ( others => '0' ) ;
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for i in rv.history'range loop
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rv.history(i) := ( others => '0' ) ;
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end loop ;
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return rv ;
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end function ;
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signal current, future : state_t := NULL_STATE ;
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begin
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quiet <= current.quiet ;
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sync : process( clock )
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begin
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if( reset = '1' ) then
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current <= NULL_STATE ;
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elsif( rising_edge( clock ) ) then
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current <= future ;
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end if ;
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end process ;
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comb: process(all)
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begin
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future <= current ;
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case current.fsm is
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when IDLE =>
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future.fsm <= CAPTURE_PHY_NOISE ;
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future.quiet <= '0' ;
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when CAPTURE_PHY_NOISE =>
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future.quiet <= '0' ;
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--if( current.timer > 100000 ) then
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if( current.timer > 110 ) then
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future.fsm <= CSMA ;
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future.powersum <= ( others => '0' ) ;
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for i in future.history'range loop
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future.history(i) <= ( others => '0' ) ;
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end loop ;
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future.timer <= ( others => '0' ) ;
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end if ;
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if( in_sample.valid = '1' ) then
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future.timer <= current.timer + 1 ;
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for i in 0 to current.history'high - 1 loop
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future.history( i + 1 ) <= current.history( i ) ;
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end loop ;
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future.history(0) <= unsigned(resize(in_sample.i * in_sample.i + in_sample.q * in_sample.q, 32 ));
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future.powersum <= current.powersum + current.history(0)
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- current.history(79);
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if( current.timer > 100 ) then
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if( current.powersum < current.min_phy_noise ) then
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future.min_phy_noise <= current.powersum ;
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end if ;
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end if ;
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end if ;
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when CSMA =>
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if( in_sample.valid = '1' ) then
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for i in 0 to current.history'high - 1 loop
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future.history( i + 1 ) <= current.history( i ) ;
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end loop ;
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future.history(0) <= unsigned(resize(in_sample.i * in_sample.i + in_sample.q * in_sample.q, 32 ));
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future.powersum <= current.powersum + current.history(0)
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- current.history(9);
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if( current.timer > 20 ) then
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if( (current.min_phy_noise / 8 ) * 4 > current.powersum ) then
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future.quiet <= '1' ;
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else
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future.quiet <= '0' ;
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end if ;
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else
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future.timer <= current.timer + 1 ;
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end if ;
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end if ;
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end case ;
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end process ;
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end architecture ;
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