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https://github.com/Nuand/bladeRF-wiphy.git
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76 lines
2.4 KiB
VHDL
76 lines
2.4 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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use ieee.math_real.all ;
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library wlan ;
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use wlan.wlan_p.all ;
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use wlan.wlan_rx_p.all ;
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use wlan.cordic_p.all ;
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use wlan.nco_p.all ;
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entity wlan_cfo_correction is
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port (
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clock : in std_logic ;
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reset : in std_logic ;
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dphase : in signed( 15 downto 0 ) ;
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dphase_valid : in std_logic ;
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p_mag : in signed( 23 downto 0 ) ;
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p_mag_valid : in std_logic ;
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in_sample : in wlan_sample_t ;
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out_sample : out wlan_sample_t
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) ;
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end entity;
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architecture arch of wlan_cfo_correction is
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signal nco_inputs : nco_input_t ;
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signal nco_outputs : nco_output_t ;
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begin
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U_nco : entity work.nco
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port map (
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clock => clock,
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reset => reset,
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inputs => nco_inputs,
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outputs => nco_outputs
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) ;
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process( clock )
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begin
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if( rising_edge( clock ) ) then
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nco_inputs.valid <= in_sample.valid ;
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out_sample.valid <= in_sample.valid ;
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if( in_sample.valid = '1' ) then
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if( p_mag_valid = '0' ) then
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out_sample.i <= in_sample.i ;
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out_sample.q <= in_sample.q ;
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else
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out_sample.i <= resize( shift_right( in_sample.i * p_mag , 15 ), 16 ) ;
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out_sample.q <= resize( shift_right( in_sample.q * p_mag , 15 ), 16 ) ;
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end if ;
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end if ;
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end if ;
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end process ;
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end architecture ;
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