mirror of
https://github.com/Nuand/bladeRF-wiphy.git
synced 2024-12-18 21:28:06 +00:00
234 lines
6.8 KiB
VHDL
234 lines
6.8 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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library work ;
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use work.wlan_p.all ;
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use work.wlan_tx_p.all ;
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entity wlan_tx_controller is
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port (
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clock : in std_logic ;
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reset : in std_logic ;
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-- Control from the MAC
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tx_vector : in wlan_tx_vector_t ;
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tx_vector_valid : in std_logic ;
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-- Caculated parameters
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params : out wlan_tx_params_t ;
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params_valid : out std_logic ;
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-- TX status generation
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status : out wlan_tx_status_t ;
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status_valid : out std_logic ;
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-- Encoder from MAC
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encoder_start : out std_logic ;
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encoder_done : in std_logic ;
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-- Short preamble control and status
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short_start : out std_logic ;
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short_done : in std_logic ;
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-- Long preamble control and status
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long_done : in std_logic ;
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-- Modulator control and status
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mod_init : out std_logic ;
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mod_end : in std_logic ;
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-- TX done
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tx_done : in std_logic
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) ;
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end entity ;
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architecture arch of wlan_tx_controller is
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type fsm_t is (IDLE, START_TRANSMISSION, START_ENCODING_DATA, WAIT_FOR_PREAMBLE_DONE, WAIT_FOR_TX_DONE) ;
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type state_t is record
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fsm : fsm_t ;
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params : wlan_tx_params_t ;
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params_valid : std_logic ;
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short_start : std_logic ;
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encoder_start : std_logic ;
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mod_init : std_logic ;
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status_valid : std_logic ;
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end record ;
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function calculate_params( x : wlan_tx_vector_t ) return wlan_tx_params_t is
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variable rv : wlan_tx_params_t ;
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begin
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rv.datarate := x.datarate ;
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rv.length := x.length ;
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rv.lfsr_init := "1011101" ;
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case x.datarate is
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when WLAN_RATE_6 =>
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-- BPSK R=1/2
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rv.n_bpsc := 1 ;
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rv.n_dbps := 24 ;
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rv.n_cbps := 48 ;
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rv.modulation := WLAN_BPSK ;
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when WLAN_RATE_9 =>
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-- BPSK R=3/4
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rv.n_bpsc := 1 ;
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rv.n_dbps := 36 ;
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rv.n_cbps := 48 ;
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rv.modulation := WLAN_BPSK ;
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when WLAN_RATE_12 =>
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-- QPSK R=1/2
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rv.n_bpsc := 2 ;
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rv.n_dbps := 48 ;
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rv.n_cbps := 96 ;
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rv.modulation := WLAN_QPSK ;
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when WLAN_RATE_18 =>
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-- QPSK R=3/4
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rv.n_bpsc := 2 ;
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rv.n_dbps := 72 ;
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rv.n_cbps := 96 ;
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rv.modulation := WLAN_QPSK ;
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when WLAN_RATE_24 =>
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-- 16-QAM R=1/2
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rv.n_bpsc := 4 ;
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rv.n_dbps := 96 ;
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rv.n_cbps := 192 ;
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rv.modulation := WLAN_16QAM ;
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when WLAN_RATE_36 =>
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-- 16-QAM R=3/4
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rv.n_bpsc := 4 ;
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rv.n_dbps := 144 ;
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rv.n_cbps := 192 ;
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rv.modulation := WLAN_16QAM ;
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when WLAN_RATE_48 =>
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-- 64-QAM R=2/3
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rv.n_bpsc := 6 ;
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rv.n_dbps := 192 ;
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rv.n_cbps := 288 ;
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rv.modulation := WLAN_64QAM ;
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when WLAN_RATE_54 =>
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-- 64-QAM R=3/4
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rv.n_bpsc := 6 ;
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rv.n_dbps := 216 ;
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rv.n_cbps := 288;
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rv.modulation := WLAN_64QAM ;
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when others =>
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report "Invalid params" severity failure ;
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end case ;
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case x.bandwidth is
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when WLAN_BW_5 =>
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null ;
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when WLAN_BW_10 =>
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null ;
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when WLAN_BW_20 =>
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null ;
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when others =>
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report "Invalid bandwidth" severity failure ;
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end case ;
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return rv ;
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end function ;
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function NULL_STATE return state_t is
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variable rv : state_t ;
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begin
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rv.fsm := IDLE ;
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rv.params_valid := '0' ;
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rv.short_start := '0' ;
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rv.encoder_start := '0' ;
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rv.mod_init := '0' ;
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rv.status_valid := '0' ;
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return rv ;
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end function ;
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signal current, future : state_t := NULL_STATE ;
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begin
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params <= current.params ;
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params_valid <= current.params_valid ;
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short_start <= current.short_start ;
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encoder_start <= current.encoder_start ;
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mod_init <= current.mod_init ;
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sync : process(clock, reset)
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begin
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if( reset = '1' ) then
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current <= NULL_STATE ;
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elsif( rising_edge(clock) ) then
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current <= future ;
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end if ;
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end process ;
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comb : process(all)
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begin
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future <= current ;
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future.params_valid <= '0' ;
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future.short_start <= '0' ;
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future.encoder_start <= '0' ;
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future.mod_init <= '0' ;
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future.status_valid <= '0' ;
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case current.fsm is
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when IDLE =>
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future.params_valid <= tx_vector_valid ;
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if( tx_vector_valid = '1' ) then
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future.params <= calculate_params(tx_vector) ;
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future.fsm <= START_TRANSMISSION ;
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end if ;
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when START_TRANSMISSION =>
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future.short_start <= '1' ;
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future.fsm <= START_ENCODING_DATA ;
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when START_ENCODING_DATA =>
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future.fsm <= WAIT_FOR_PREAMBLE_DONE ;
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when WAIT_FOR_PREAMBLE_DONE =>
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if( long_done = '1' ) then
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future.fsm <= WAIT_FOR_TX_DONE ;
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future.encoder_start <= '1' ;
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future.mod_init <= '1' ;
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end if ;
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when WAIT_FOR_TX_DONE =>
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if( tx_done = '1' ) then
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future.fsm <= IDLE ;
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end if ;
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end case ;
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end process ;
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end architecture ;
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