mirror of
https://github.com/Nuand/bladeRF-wiphy.git
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133 lines
4.5 KiB
VHDL
133 lines
4.5 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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library wlan ;
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use wlan.wlan_p.all ;
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use wlan.wlan_rx_p.all ;
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entity wlan_dsss_demodulator is
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port (
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clock : in std_logic ;
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reset : in std_logic ;
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modulation : in wlan_modulation_t ;
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in_bin_idx : in natural ;
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despread : in wlan_sample_t ;
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out_bin_idx : out natural ;
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out_bits : out std_logic_vector( 1 downto 0 ) ;
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out_valid : out std_logic
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) ;
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end entity ;
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architecture arch of wlan_dsss_demodulator is
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signal history : sample_array_t( 19 downto 0 );
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signal res_i : signed( 19 downto 0 ) ;
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signal a_i, a_q, b_i, b_q : signed(15 downto 0) ;
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signal res_q : signed( 19 downto 0 ) ;
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signal res_valid : std_logic ;
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signal coded_bits : std_logic_vector( 1 downto 0 ) ;
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signal coded_valid : std_logic ;
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signal coded_idx : natural ;
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signal decoded_bits : std_logic_vector( 19 downto 0 ) ;
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signal demod_bits : std_logic_vector( 19 downto 0 ) ;
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type bit_history_t is array(0 to 20) of std_logic_vector(7 downto 0) ;
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signal bit_history : bit_history_t ;
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begin
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-- demodulate bits
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process( clock )
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variable wtf : signed (19 downto 0 );
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begin
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if( reset = '1' ) then
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history <= ( others => NULL_SAMPLE ) ;
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coded_bits <= ( others => '0' ) ;
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coded_valid <= '0' ;
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coded_idx <= 0 ;
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demod_bits <= ( others => '0' ) ;
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elsif( rising_edge( clock ) ) then
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coded_valid <= '0' ;
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if( despread.valid = '1' ) then
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for i in 0 to history'high - 1 loop
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history(i+1) <= history(i) ;
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end loop ;
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history(0) <= despread ;
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if( modulation = WLAN_DBPSK ) then
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coded_idx <= in_bin_idx ;
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a_i <= despread.i;
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a_q <= history(19).i;
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b_i <= despread.q;
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b_q <= history(19).q;
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wtf := resize((shift_right(despread.i * history(19).i,4) + shift_right(despread.q * history(19).q,4)), 20);
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res_i <= wtf;
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if( wtf < 0 ) then
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demod_bits(in_bin_idx) <= '1' ;
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coded_bits(0) <= '1' ;
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else
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demod_bits(in_bin_idx) <= '0' ;
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coded_bits(0) <= '0' ;
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end if ;
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coded_valid <= '1' ;
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end if ;
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end if ;
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end if ;
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end process ;
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-- descramble decoded bits
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process( clock )
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begin
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if( reset = '1' ) then
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out_bin_idx <= 0 ;
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out_bits <= ( others => '0' ) ;
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out_valid <= '0' ;
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bit_history <= ( others => ( others => '0' ) ) ;
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decoded_bits<= ( others => '0' ) ;
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elsif( rising_edge( clock ) ) then
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out_valid <= '0' ;
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if( coded_valid = '1' ) then
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if( modulation = WLAN_DBPSK ) then
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-- save per bin descrambler register
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bit_history(coded_idx) <= bit_history(coded_idx)(6 downto 0) & coded_bits(0) ;
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-- descramble bit
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out_bits(0) <= coded_bits(0) xor bit_history(coded_idx)(3) xor bit_history(coded_idx)(6) ;
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decoded_bits(coded_idx) <= coded_bits(0) xor bit_history(coded_idx)(3) xor bit_history(coded_idx)(6) ;
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out_bin_idx <= coded_idx ;
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out_valid <= '1' ;
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end if ;
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end if ;
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end if ;
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end process ;
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end architecture ;
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