mirror of
https://github.com/Nuand/bladeRF-wiphy.git
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222 lines
7.1 KiB
VHDL
222 lines
7.1 KiB
VHDL
-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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use ieee.math_real.all ;
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entity wlan_agc is
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port (
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-- 40MHz clock and async asserted, sync deasserted reset
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clock : in std_logic ;
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reset : in std_logic ;
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agc_hold_req : in std_logic ;
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gain_inc_req : out std_logic ;
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gain_dec_req : out std_logic ;
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gain_rst_req : out std_logic ;
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gain_ack : in std_logic ;
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gain_nack : in std_logic ;
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gain_max : in std_logic ;
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rst_gains : out std_logic ;
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burst : out std_logic ;
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sample_i : in signed(15 downto 0 ) ;
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sample_q : in signed(15 downto 0 ) ;
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sample_valid : in std_logic
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) ;
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end entity ;
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architecture arch of wlan_agc is
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type wlan_sample_t is record
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i : signed(15 downto 0) ;
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q : signed(15 downto 0) ;
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valid : std_logic ;
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end record ;
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signal iir : signed( 31 downto 0 ) ;
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signal ptemp : signed( 31 downto 0 ) ;
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signal burst_cnt: signed( 7 downto 0 ) ;
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function run_iir( x : signed( 31 downto 0); y : signed ( 31 downto 0) )
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return signed
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is
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variable amrea : signed(31 downto 0) ;
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begin
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amrea := resize( x - shift_right(x, 6) + shift_right(y, 6), 32 );
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return amrea;
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end;
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type fsm_t is (IDLE, SETTLE, ATTACK, WAIT_GAIN_ACK, WAIT_GAIN_ACK_1, HOLD) ;
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type state_t is record
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fsm : fsm_t ;
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inc_req : std_logic ;
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dec_req : std_logic ;
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rst_req : std_logic ;
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timer : unsigned( 10 downto 0 ) ;
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end record ;
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function NULL_STATE return state_t is
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variable rv : state_t ;
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begin
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rv.fsm := IDLE ;
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rv.inc_req := '0' ;
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rv.dec_req := '0' ;
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rv.rst_req := '0' ;
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rv.timer := ( others => '0' );
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return rv ;
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end function ;
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signal current, future : state_t := NULL_STATE ;
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signal sample, sample_out : wlan_sample_t ;
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begin
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sample.i <= sample_i;
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sample.q <= sample_q;
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sample.valid <= sample_valid;
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gain_inc_req <= current.inc_req ;
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gain_dec_req <= current.dec_req ;
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gain_rst_req <= current.rst_req ;
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process( clock )
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begin
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if( reset = '1' ) then
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rst_gains <= '0' ;
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burst <= '0' ;
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elsif( rising_edge( clock )) then
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if( ( gain_max = '1' and iir < 4200 ) or current.fsm = SETTLE ) then
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rst_gains <= '1' ;
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else
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rst_gains <= '0' ;
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end if ;
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if( gain_max = '0' or iir > 150000 ) then
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burst <= '1' ;
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burst_cnt <= to_signed(18, burst_cnt'length) ;
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else
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if( ptemp > 300000 ) then
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burst <= '1' ;
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burst_cnt <= to_signed(6, burst_cnt'length) ;
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else
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if( burst_cnt > 0 ) then
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burst <= '1' ;
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burst_cnt <= burst_cnt - 1 ;
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else
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burst <= '0' ;
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end if ;
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end if ;
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end if ;
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end if ;
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end process ;
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process( clock )
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begin
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if( reset = '1' ) then
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iir <= ( others => '0' ) ;
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ptemp <= (others => '0' ) ;
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elsif( rising_edge( clock )) then
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if( current.timer = 18 ) then
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iir <= ptemp ;
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elsif( sample.valid = '1') then
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ptemp <= sample.i * sample.i + sample.q * sample.q ;
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iir <= run_iir(iir, ptemp) ;
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end if ;
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end if ;
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end process ;
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sync : process(clock, reset)
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begin
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if( reset = '1' ) then
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current <= NULL_STATE ;
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elsif( rising_edge(clock) ) then
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current <= future ;
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end if ;
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end process ;
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comb : process(all)
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begin
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future <= current ;
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future.inc_req <= '0' ;
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future.dec_req <= '0' ;
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future.rst_req <= '0' ;
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case current.fsm is
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when IDLE =>
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future.fsm <= SETTLE ;
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when SETTLE =>
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if( current.timer > 32 ) then -- 50 looks good 70 is overkill
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future.timer <= ( others => '0' ) ;
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future.fsm <= ATTACK ;
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else
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if( current.timer < 400 ) then
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future.timer <= current.timer + 1 ;
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end if ;
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end if ;
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when ATTACK =>
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if( rst_gains = '1' ) then
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future.timer <= ( others => '0' ) ;
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elsif( current.timer < 1000 ) then
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future.timer <= current.timer + 1 ;
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end if ;
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if( agc_hold_req = '1' ) then
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future.fsm <= HOLD ;
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else
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-- 405000, -48dBm to enter mid, -28dBm to enter low
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if( current.timer < 24 and iir > 485000 ) then --335000
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-- I = Q = sqrt(2048*2048/10)=657, IIR = I^2 + Q^2= 845000
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future.fsm <= WAIT_GAIN_ACK ;
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future.dec_req <= '1' ;
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elsif( current.timer > 300 and iir < 1000 ) then
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--elsif( iir < 5000 ) then
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-- I = Q = 50, IIR = I^2 + Q^2= 5000
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future.inc_req <= '1' ;
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future.fsm <= WAIT_GAIN_ACK ;
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end if ;
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end if ;
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when WAIT_GAIN_ACK =>
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future.fsm <= WAIT_GAIN_ACK_1 ;
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when WAIT_GAIN_ACK_1 =>
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if( gain_ack = '1' ) then
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future.fsm <= SETTLE ;
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future.timer <= ( others => '0' ) ;
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end if ;
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if( gain_nack = '1' ) then
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future.fsm <= ATTACK ;
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end if ;
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when HOLD =>
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if( iir < 5000 ) then
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-- I = Q = 50, IIR = I^2 + Q^2= 5000
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future.rst_req <= '1' ;
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future.fsm <= WAIT_GAIN_ACK ;
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end if ;
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end case ;
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end process ;
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end architecture ;
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